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Update golden results with new lib syntax

This commit is contained in:
Matt Guthaus 2020-04-22 10:40:04 -07:00
parent c2419af2e2
commit 14f440df73
10 changed files with 583 additions and 400 deletions
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47
compiler/tests/21_hspice_delay_test.py
View File

@ -60,29 +60,36 @@ class timing_sram_test(openram_test):
data, port_data = d.analyze(probe_address, probe_data, slews, loads)
#Combine info about port into all data
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2383338],
'delay_lh': [0.2383338],
'leakage_power': 0.0014532999999999998,
'min_period': 0.898,
'read0_power': [0.30059800000000003],
'read1_power': [0.30061810000000005],
'slew_hl': [0.25358420000000004],
'slew_lh': [0.25358420000000004],
'write0_power': [0.34616749999999996],
'write1_power': [0.2792924]}
golden_data = {'min_period': 0.898,
'write1_power': [0.2659137999999999],
'disabled_write0_power': [0.1782495],
'disabled_read0_power': [0.14490679999999997],
'write0_power': [0.3330119],
'disabled_write1_power': [0.1865223],
'leakage_power': 0.0014532,
'disabled_read1_power': [0.1627516],
'slew_lh': [0.25367799999999996],
'slew_hl': [0.25367799999999996],
'delay_lh': [0.23820930000000004],
'delay_hl': [0.23820930000000004],
'read1_power': [0.3005756],
'read0_power': [0.3005888]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.7448],
'delay_lh': [1.7448],
'leakage_power': 0.0006356744000000001,
golden_data = {'leakage_power': 0.0006356576000000001,
'write1_power': [11.292700000000002],
'read0_power': [12.98],
'disabled_write1_power': [8.3707],
'write0_power': [14.4447], 'delay_hl': [1.7445000000000002],
'disabled_read0_power': [6.4325],
'slew_hl': [1.7437],
'disabled_write0_power': [8.1307],
'slew_lh': [1.7437],
'read1_power': [12.9869],
'disabled_read1_power': [7.706],
'min_period': 6.25,
'read0_power': [12.9846],
'read1_power': [12.9722],
'slew_hl': [1.7433],
'slew_lh': [1.7433],
'write0_power': [14.8772],
'write1_power': [11.7217]}
'delay_lh': [1.7445000000000002]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results

44
compiler/tests/21_ngspice_delay_test.py
View File

@ -55,27 +55,35 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2264205],
'delay_lh': [0.2264205],
'leakage_power': 0.0021017429999999997,
'min_period': 0.859,
'read0_power': [0.3339161],
'read1_power': [0.31329440000000003],
'slew_hl': [0.2590786],
'slew_lh': [0.2590786],
'write0_power': [0.36360849999999995],
'write1_power': [0.3486931]}
golden_data = {'slew_lh': [0.2592187],
'slew_hl': [0.2592187],
'delay_lh': [0.2465583],
'disabled_write0_power': [0.1924678],
'disabled_read0_power': [0.152483],
'write0_power': [0.3409064],
'disabled_read1_power': [0.1737818],
'read0_power': [0.3096708],
'read1_power': [0.3107916],
'delay_hl': [0.2465583],
'write1_power': [0.26915849999999997],
'leakage_power': 0.002044307,
'min_period': 0.898,
'disabled_write1_power': [0.201411]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.85985],
'delay_lh': [1.85985],
golden_data = {'read1_power': [12.11658],
'write1_power': [10.52653],
'read0_power': [11.956710000000001],
'disabled_write0_power': [7.673665],
'disabled_write1_power': [7.981922000000001],
'slew_lh': [1.868836],
'slew_hl': [1.868836],
'delay_hl': [1.8598510000000001],
'delay_lh': [1.8598510000000001],
'leakage_power': 0.008613619,
'disabled_read0_power': [5.904712],
'min_period': 6.875,
'read0_power': [12.656310000000001],
'read1_power': [12.11682],
'slew_hl': [1.868942],
'slew_lh': [1.868942],
'write0_power': [13.978110000000001],
'write1_power': [11.437930000000001]}
'disabled_read1_power': [7.132159],
'write0_power': [13.406400000000001]}
else:
self.assertTrue(False) # other techs fail

83
compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 1.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
index_2("5.2275e-05, 0.0002091, 0.0008364");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 1124.88;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000167;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
max_capacitance : 0.0008364000000000001;
min_capacitance : 5.2275000000000003e-05;
memory_read(){
address : addr0;
}
@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.088, 0.088, 0.088",\
"0.088, 0.088, 0.088",\
"0.088, 0.088, 0.088");
values("0.193, 0.193, 0.194",\
"0.193, 0.193, 0.194",\
"0.193, 0.193, 0.194");
}
cell_fall(CELL_TABLE) {
values("0.088, 0.088, 0.088",\
"0.088, 0.088, 0.088",\
"0.088, 0.088, 0.088");
values("0.193, 0.193, 0.194",\
"0.193, 0.193, 0.194",\
"0.193, 0.193, 0.194");
}
rise_transition(CELL_TABLE) {
values("0.001, 0.001, 0.001",\
@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
max_transition : 0.04;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
pin(csb0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
pin(web0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
pin(clk0){
clock : true;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("0.033101244168888884");
values("9.240667e-02");
}
fall_power(scalar){
values("0.033101244168888884");
values("9.240667e-02");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("0.033101244168888884");
values("9.240667e-02");
}
fall_power(scalar){
values("0.033101244168888884");
values("9.240667e-02");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("9.240667e-02");
}
fall_power(scalar){
values("0");
values("9.240667e-02");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("9.240667e-02");
}
fall_power(scalar){
values("9.240667e-02");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.009");
values("0.0195");
}
fall_constraint(scalar) {
values("0.009");
values("0.0195");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0.018");
values("0.039");
}
fall_constraint(scalar) {
values("0.018");
values("0.039");
}
}
}

83
compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 1.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
index_2("5.2275e-05, 0.0002091, 0.0008364");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 1124.88;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000167;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
max_capacitance : 0.0008364000000000001;
min_capacitance : 5.2275000000000003e-05;
memory_read(){
address : addr0;
}
@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.107, 0.107, 0.107",\
"0.107, 0.107, 0.107",\
"0.107, 0.107, 0.107");
values("0.236, 0.236, 0.237",\
"0.236, 0.236, 0.237",\
"0.236, 0.236, 0.237");
}
cell_fall(CELL_TABLE) {
values("0.107, 0.107, 0.107",\
"0.107, 0.107, 0.107",\
"0.107, 0.107, 0.107");
values("0.236, 0.236, 0.237",\
"0.236, 0.236, 0.237",\
"0.236, 0.236, 0.237");
}
rise_transition(CELL_TABLE) {
values("0.001, 0.001, 0.001",\
@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
max_transition : 0.04;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
pin(csb0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
pin(web0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
pin(clk0){
clock : true;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("0.033101244168888884");
values("7.560546e-02");
}
fall_power(scalar){
values("0.033101244168888884");
values("7.560546e-02");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("0.033101244168888884");
values("7.560546e-02");
}
fall_power(scalar){
values("0.033101244168888884");
values("7.560546e-02");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("7.560546e-02");
}
fall_power(scalar){
values("0");
values("7.560546e-02");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("7.560546e-02");
}
fall_power(scalar){
values("7.560546e-02");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.0105");
values("0.0235");
}
fall_constraint(scalar) {
values("0.0105");
values("0.0235");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0.021");
values("0.047");
}
fall_constraint(scalar) {
values("0.021");
values("0.047");
}
}
}

167
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 1.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
index_2("5.2275e-05, 0.0002091, 0.0008364");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 977.4951374999999;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.0011164579999999999;
value : 0.00163;
}
cell_leakage_power : 0;
cell_leakage_power : 0.00163;
bus(din0){
bus_type : data;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -98,9 +110,9 @@ cell (sram_2_16_1_freepdk45){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039");
values("0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.027, 0.027, 0.033",\
@ -112,14 +124,14 @@ cell (sram_2_16_1_freepdk45){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022");
values("-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016");
values("-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016");
}
}
}
@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
max_capacitance : 0.0008364000000000001;
min_capacitance : 5.2275000000000003e-05;
memory_read(){
address : addr0;
}
@ -138,24 +150,24 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.235, 0.235, 0.239",\
"0.235, 0.236, 0.24",\
"0.241, 0.242, 0.246");
values("0.226, 0.227, 0.232",\
"0.227, 0.228, 0.233",\
"0.232, 0.234, 0.238");
}
cell_fall(CELL_TABLE) {
values("2.583, 2.585, 2.612",\
"2.584, 2.585, 2.613",\
"2.59, 2.592, 2.62");
values("0.226, 0.227, 0.232",\
"0.227, 0.228, 0.233",\
"0.232, 0.234, 0.238");
}
rise_transition(CELL_TABLE) {
values("0.022, 0.022, 0.03",\
"0.022, 0.023, 0.03",\
"0.022, 0.022, 0.03");
values("0.256, 0.256, 0.257",\
"0.256, 0.256, 0.257",\
"0.256, 0.256, 0.257");
}
fall_transition(CELL_TABLE) {
values("0.078, 0.079, 0.083",\
"0.078, 0.079, 0.083",\
"0.079, 0.079, 0.083");
values("0.256, 0.256, 0.257",\
"0.256, 0.256, 0.257",\
"0.256, 0.256, 0.257");
}
}
}
@ -164,16 +176,16 @@ cell (sram_2_16_1_freepdk45){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
max_transition : 0.04;
pin(addr0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039");
values("0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.027, 0.027, 0.033",\
@ -185,14 +197,14 @@ cell (sram_2_16_1_freepdk45){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022");
values("-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016");
values("-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016");
}
}
}
@ -200,14 +212,14 @@ cell (sram_2_16_1_freepdk45){
pin(csb0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039");
values("0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.027, 0.027, 0.033",\
@ -219,28 +231,28 @@ cell (sram_2_16_1_freepdk45){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022");
values("-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016");
values("-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016");
}
}
}
pin(web0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039",\
"0.033, 0.033, 0.039");
values("0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033",\
"0.033, 0.033, 0.033");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.027, 0.027, 0.033",\
@ -252,14 +264,14 @@ cell (sram_2_16_1_freepdk45){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022",\
"-0.01, -0.016, -0.022");
values("-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021",\
"-0.01, -0.01, 0.021");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016",\
"-0.016, -0.016, -0.016");
values("-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016",\
"-0.016, -0.01, -0.016");
}
}
}
@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
pin(clk0){
clock : true;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("0.03599689694444445");
values("3.069977e-01");
}
fall_power(scalar){
values("0.03599689694444445");
values("3.686680e-01");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("0.029906643888888886");
values("2.055845e-01");
}
fall_power(scalar){
values("0.029906643888888886");
values("1.933561e-01");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("3.315565e-01");
}
fall_power(scalar){
values("0");
values("3.314553e-01");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("1.777355e-01");
}
fall_power(scalar){
values("1.615044e-01");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("2.422");
values("0.449");
}
fall_constraint(scalar) {
values("2.422");
values("0.449");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("4.844");
values("0.898");
}
fall_constraint(scalar) {
values("4.844");
values("0.898");
}
}
}

83
compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 1.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.00125, 0.005, 0.04");
index_2("0.052275, 0.2091, 1.6728");
index_2("5.2275e-05, 0.0002091, 0.0008364");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_freepdk45){
dont_use : true;
map_only : true;
dont_touch : true;
area : 977.4951374999999;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000179;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_freepdk45){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 1.6728;
min_capacitance : 0.052275;
max_capacitance : 0.0008364000000000001;
min_capacitance : 5.2275000000000003e-05;
memory_read(){
address : addr0;
}
@ -138,14 +150,14 @@ cell (sram_2_16_1_freepdk45){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.098, 0.098, 0.098",\
"0.098, 0.098, 0.098",\
"0.098, 0.098, 0.098");
values("0.215, 0.215, 0.216",\
"0.215, 0.215, 0.216",\
"0.215, 0.215, 0.216");
}
cell_fall(CELL_TABLE) {
values("0.098, 0.098, 0.098",\
"0.098, 0.098, 0.098",\
"0.098, 0.098, 0.098");
values("0.215, 0.215, 0.216",\
"0.215, 0.215, 0.216",\
"0.215, 0.215, 0.216");
}
rise_transition(CELL_TABLE) {
values("0.001, 0.001, 0.001",\
@ -164,7 +176,7 @@ cell (sram_2_16_1_freepdk45){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
max_transition : 0.04;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_freepdk45){
pin(csb0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_freepdk45){
pin(web0){
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_freepdk45){
pin(clk0){
clock : true;
direction : input;
capacitance : 0.2091;
capacitance : 0.00020910000000000001;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("0.0747594982142222");
values("8.316600e-02");
}
fall_power(scalar){
values("0.0747594982142222");
values("8.316600e-02");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("0.0747594982142222");
values("8.316600e-02");
}
fall_power(scalar){
values("0.0747594982142222");
values("8.316600e-02");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("8.316600e-02");
}
fall_power(scalar){
values("0");
values("8.316600e-02");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("8.316600e-02");
}
fall_power(scalar){
values("8.316600e-02");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.0");
values("0.0215");
}
fall_constraint(scalar) {
values("0.0");
values("0.0215");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0");
values("0.043");
}
fall_constraint(scalar) {
values("0");
values("0.043");
}
}
}

95
compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 5.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
index_2("0.00245605, 0.0098242, 0.0392968");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 73068.14000000001;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000167;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
max_capacitance : 0.0392968;
min_capacitance : 0.00245605;
memory_read(){
address : addr0;
}
@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.241, 0.241, 0.241",\
"0.241, 0.241, 0.241",\
"0.241, 0.241, 0.241");
values("1.183, 1.199, 1.264",\
"1.183, 1.199, 1.264",\
"1.183, 1.199, 1.264");
}
cell_fall(CELL_TABLE) {
values("0.241, 0.241, 0.241",\
"0.241, 0.241, 0.241",\
"0.241, 0.241, 0.241");
values("1.183, 1.199, 1.264",\
"1.183, 1.199, 1.264",\
"1.183, 1.199, 1.264");
}
rise_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.006, 0.007, 0.014",\
"0.006, 0.007, 0.014",\
"0.006, 0.007, 0.014");
}
fall_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.006, 0.007, 0.014",\
"0.006, 0.007, 0.014",\
"0.006, 0.007, 0.014");
}
}
}
@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
max_transition : 0.4;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(csb0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(web0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
pin(clk0){
clock : true;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("4.99880645");
values("7.797263e+00");
}
fall_power(scalar){
values("4.99880645");
values("7.797263e+00");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("4.99880645");
values("7.797263e+00");
}
fall_power(scalar){
values("4.99880645");
values("7.797263e+00");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("7.797263e+00");
}
fall_power(scalar){
values("0");
values("7.797263e+00");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("7.797263e+00");
}
fall_power(scalar){
values("7.797263e+00");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.024");
values("0.1265");
}
fall_constraint(scalar) {
values("0.024");
values("0.1265");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0.048");
values("0.253");
}
fall_constraint(scalar) {
values("0.048");
values("0.253");
}
}
}

95
compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 5.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
index_2("0.00245605, 0.0098242, 0.0392968");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 73068.14000000001;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000167;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
max_capacitance : 0.0392968;
min_capacitance : 0.00245605;
memory_read(){
address : addr0;
}
@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.294, 0.294, 0.294",\
"0.294, 0.294, 0.294",\
"0.294, 0.294, 0.294");
values("1.446, 1.466, 1.545",\
"1.446, 1.466, 1.545",\
"1.446, 1.466, 1.545");
}
cell_fall(CELL_TABLE) {
values("0.294, 0.294, 0.294",\
"0.294, 0.294, 0.294",\
"0.294, 0.294, 0.294");
values("1.446, 1.466, 1.545",\
"1.446, 1.466, 1.545",\
"1.446, 1.466, 1.545");
}
rise_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.007, 0.009, 0.017",\
"0.007, 0.009, 0.017",\
"0.007, 0.009, 0.017");
}
fall_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.007, 0.009, 0.017",\
"0.007, 0.009, 0.017",\
"0.007, 0.009, 0.017");
}
}
}
@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
max_transition : 0.4;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(csb0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(web0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
pin(clk0){
clock : true;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("4.99880645");
values("6.379579e+00");
}
fall_power(scalar){
values("4.99880645");
values("6.379579e+00");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("4.99880645");
values("6.379579e+00");
}
fall_power(scalar){
values("4.99880645");
values("6.379579e+00");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("6.379579e+00");
}
fall_power(scalar){
values("0");
values("6.379579e+00");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("6.379579e+00");
}
fall_power(scalar){
values("6.379579e+00");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.0295");
values("0.1545");
}
fall_constraint(scalar) {
values("0.0295");
values("0.1545");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0.059");
values("0.309");
}
fall_constraint(scalar) {
values("0.059");
values("0.309");
}
}
}

191
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 5.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
index_2("0.00245605, 0.0098242, 0.0392968");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 60774.3;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.0009813788999999999;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -98,28 +110,28 @@ cell (sram_2_16_1_scn4m_subm){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
max_capacitance : 0.0392968;
min_capacitance : 0.00245605;
memory_read(){
address : addr0;
}
@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("1.556, 1.576, 1.751",\
"1.559, 1.579, 1.754",\
"1.624, 1.643, 1.819");
values("1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404");
}
cell_fall(CELL_TABLE) {
values("3.445, 3.504, 3.926",\
"3.448, 3.507, 3.93",\
"3.49, 3.549, 3.972");
values("1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404");
}
rise_transition(CELL_TABLE) {
values("0.13, 0.169, 0.574",\
"0.13, 0.169, 0.574",\
"0.13, 0.169, 0.574");
values("0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015");
}
fall_transition(CELL_TABLE) {
values("0.467, 0.49, 0.959",\
"0.467, 0.49, 0.959",\
"0.47, 0.493, 0.96");
values("0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015");
}
}
}
@ -164,35 +176,35 @@ cell (sram_2_16_1_scn4m_subm){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
max_transition : 0.4;
pin(addr0[3:0]){
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
@ -200,66 +212,66 @@ cell (sram_2_16_1_scn4m_subm){
pin(csb0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
pin(web0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228",\
"0.167, 0.167, 0.228");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
fall_constraint(CONSTRAINT_TABLE) {
values("0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137",\
"0.131, 0.125, 0.137");
values("0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009",\
"0.009, 0.009, 0.009");
}
}
timing(){
timing_type : hold_rising;
related_pin : "clk0";
rise_constraint(CONSTRAINT_TABLE) {
values("-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114",\
"-0.065, -0.071, -0.114");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
fall_constraint(CONSTRAINT_TABLE) {
values("-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089",\
"-0.089, -0.089, -0.089");
values("0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001",\
"0.001, 0.001, 0.001");
}
}
}
@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
pin(clk0){
clock : true;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("9.972790277777777");
values("7.017537e+00");
}
fall_power(scalar){
values("9.972790277777777");
values("7.017537e+00");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("8.899322499999998");
values("7.017537e+00");
}
fall_power(scalar){
values("8.899322499999998");
values("7.017537e+00");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("7.017537e+00");
}
fall_power(scalar){
values("0");
values("7.017537e+00");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("7.017537e+00");
}
fall_power(scalar){
values("7.017537e+00");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("2.344");
values("0.1405");
}
fall_constraint(scalar) {
values("2.344");
values("0.1405");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("4.688");
values("0.281");
}
fall_constraint(scalar) {
values("4.688");
values("0.281");
}
}
}

95
compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib
View File

@ -35,11 +35,14 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){
default_max_fanout : 4.0 ;
default_connection_class : universal ;
voltage_map ( VDD, 5.0 );
voltage_map ( GND, 0 );
lu_table_template(CELL_TABLE){
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1("0.0125, 0.05, 0.4");
index_2("2.45605, 9.8242, 78.5936");
index_2("0.00245605, 0.0098242, 0.0392968");
}
lu_table_template(CONSTRAINT_TABLE){
@ -78,17 +81,26 @@ cell (sram_2_16_1_scn4m_subm){
dont_use : true;
map_only : true;
dont_touch : true;
area : 60774.3;
area : 0;
pg_pin(vdd) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin(gnd) {
voltage_name : GND;
pg_type : primary_ground;
}
leakage_power () {
when : "csb0";
value : 0.000179;
value : 0.000198;
}
cell_leakage_power : 0;
cell_leakage_power : 0.000198;
bus(din0){
bus_type : data;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
memory_write(){
address : addr0;
clocked_on : clk0;
@ -127,8 +139,8 @@ cell (sram_2_16_1_scn4m_subm){
bus(dout0){
bus_type : data;
direction : output;
max_capacitance : 78.5936;
min_capacitance : 2.45605;
max_capacitance : 0.0392968;
min_capacitance : 0.00245605;
memory_read(){
address : addr0;
}
@ -138,24 +150,24 @@ cell (sram_2_16_1_scn4m_subm){
related_pin : "clk0";
timing_type : falling_edge;
cell_rise(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
values("1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404");
}
cell_fall(CELL_TABLE) {
values("0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268",\
"0.268, 0.268, 0.268");
values("1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404",\
"1.314, 1.332, 1.404");
}
rise_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015");
}
fall_transition(CELL_TABLE) {
values("0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004",\
"0.004, 0.004, 0.004");
values("0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015",\
"0.006, 0.008, 0.015");
}
}
}
@ -164,7 +176,7 @@ cell (sram_2_16_1_scn4m_subm){
bus(addr0){
bus_type : addr;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
max_transition : 0.4;
pin(addr0[3:0]){
timing(){
@ -200,7 +212,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(csb0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -233,7 +245,7 @@ cell (sram_2_16_1_scn4m_subm){
pin(web0){
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
timing(){
timing_type : setup_rising;
related_pin : "clk0";
@ -267,52 +279,61 @@ cell (sram_2_16_1_scn4m_subm){
pin(clk0){
clock : true;
direction : input;
capacitance : 9.8242;
capacitance : 0.0098242;
internal_power(){
when : "!csb0 & clk0 & !web0";
when : "!csb0 & !web0";
rise_power(scalar){
values("11.3049604371");
values("7.017537e+00");
}
fall_power(scalar){
values("11.3049604371");
values("7.017537e+00");
}
}
internal_power(){
when : "!csb0 & !clk0 & web0";
when : "csb0 & !web0";
rise_power(scalar){
values("11.3049604371");
values("7.017537e+00");
}
fall_power(scalar){
values("11.3049604371");
values("7.017537e+00");
}
}
internal_power(){
when : "csb0";
when : "!csb0 & web0";
rise_power(scalar){
values("0");
values("7.017537e+00");
}
fall_power(scalar){
values("0");
values("7.017537e+00");
}
}
internal_power(){
when : "csb0 & web0";
rise_power(scalar){
values("7.017537e+00");
}
fall_power(scalar){
values("7.017537e+00");
}
}
timing(){
timing_type :"min_pulse_width";
related_pin : clk0;
rise_constraint(scalar) {
values("0.0");
values("0.1405");
}
fall_constraint(scalar) {
values("0.0");
values("0.1405");
}
}
timing(){
timing_type :"minimum_period";
related_pin : clk0;
rise_constraint(scalar) {
values("0");
values("0.281");
}
fall_constraint(scalar) {
values("0");
values("0.281");
}
}
}