luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Created wmask AND array en pin to go through to top layer.

This commit is contained in:
jsowash 2019-08-14 09:59:40 -07:00
parent aa4803f3c4
commit 0d7170eb95
5 changed files with 43 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/modules/port_data.py
View File

@ -545,7 +545,6 @@ class port_data(design.design):
self.add_path("metal2", [wdriver_sel_out_pin.center(), wdriver_sel_in_pin.center()])
def route_bitline_pins(self):
""" Add the bitline pins for the given port """
@ -582,9 +581,9 @@ class port_data(design.design):
if self.write_driver_array_inst:
if self.write_mask_and_array_inst:
for bit in range(self.num_wmasks):
wdriver_en_pin = self.write_driver_array_inst.get_pin("en_{}".format(bit))
self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit))
# self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit))
wdriver_en_pin = self.write_driver_array_inst.get_pin("en_{}".format(bit))
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=wdriver_en_pin.center())
self.add_layout_pin_rect_center(text="wdriver_sel_{0}".format(bit),
@ -594,6 +593,7 @@ class port_data(design.design):
self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en")
if self.write_mask_and_array_inst:
self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en")
def channel_route_bitlines(self, inst1, inst2, num_bits,

31
compiler/modules/write_mask_and_array.py
View File

@ -51,7 +51,7 @@ class write_mask_and_array(design.design):
self.place_and2_array()
self.add_layout_pins()
self.route_enable()
# self.route_enable()
self.add_boundary()
self.DRC_LVS()
@ -121,9 +121,12 @@ class write_mask_and_array(design.design):
offset=en_pin.center())
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=en_pin.center())
self.add_layout_pin_rect_center(text="en",
layer="metal3",
offset=en_pin.center())
if i < self.num_wmasks-1:
self.add_layout_pin(text="en",
layer="metal3",
offset=en_pin.ll(),
width = self.en_width(i),
height = en_pin.height())
wmask_out_pin = self.and2_insts[i].get_pin("Z")
self.add_layout_pin(text="wmask_out_{0}".format(i),
@ -146,14 +149,20 @@ class write_mask_and_array(design.design):
layer="metal3",
offset=pin_pos)
def en_width(self, pin):
en_pin = self.and2_insts[pin].get_pin("B")
next_en_pin = self.and2_insts[pin+1].get_pin("B")
width = next_en_pin.lr() - en_pin.ll()
return width[0]
def route_enable(self):
for i in range(self.num_wmasks-1):
en_pin = self.and2_insts[i].get_pin("B")
next_en_pin = self.and2_insts[i+1].get_pin("B")
offset = en_pin.center()
next_offset = next_en_pin.center()
self.add_path("metal3", [offset, next_offset])
# def route_enable(self):
# for i in range(self.num_wmasks-1):
# en_pin = self.and2_insts[i].get_pin("B")
# next_en_pin = self.and2_insts[i+1].get_pin("B")
# offset = en_pin.center()
# next_offset = next_en_pin.center()
# self.add_path("metal3", [offset, next_offset])
def get_cin(self):
"""Get the relative capacitance of all the input connections in the bank"""

8
compiler/sram/sram_1bank.py
View File

@ -125,11 +125,13 @@ class sram_1bank(sram_base):
-max_gap_size - self.data_dff_insts[port].height)
self.data_dff_insts[port].place(data_pos[port])
# Add the write mask flops to the left of the din flops.
# Add the write mask flops below the din flops.
if self.write_size is not None:
if port in self.write_ports:
wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
-max_gap_size - self.wmask_dff_insts[port].height)
wmask_pos[port] = vector(self.bank.bank_array_ll.x,
-max_gap_size - self.wmask_dff_insts[port].height)
# wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
# -max_gap_size - self.wmask_dff_insts[port].height)
self.wmask_dff_insts[port].place(wmask_pos[port])

2
compiler/sram/sram_base.py
View File

@ -501,7 +501,7 @@ class sram_base(design, verilog, lef):
temp.append("clk{}".format(port))
temp.append("rbl_bl{}".format(port))
# Ouputs
# Outputs
if port in self.read_ports:
temp.append("s_en{}".format(port))
if port in self.write_ports:

28
compiler/tests/10_write_driver_array_wmask_test.py
View File

@ -20,7 +20,7 @@ import debug
class write_driver_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
globals.init("config_{0}".format(OPTS.tech_name))
# check write driver array for single port
debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
@ -36,19 +36,19 @@ class write_driver_test(openram_test):
self.local_check(a)
# check write driver array for multi-port
# OPTS.bitcell = "pbitcell"
# OPTS.num_rw_ports = 1
# OPTS.num_w_ports = 0
# OPTS.num_r_ports = 0
#
# factory.reset()
# debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
# a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
# self.local_check(a)
#
# debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
# a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
# self.local_check(a)
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
factory.reset()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8, write_size=4)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8, write_size=4 (multi-port case)")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8, write_size=4)
self.local_check(a)
globals.end_openram()