mirror of https://github.com/VLSIDA/OpenRAM.git
Added port specification.
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@ -24,15 +24,15 @@ class write_mask_and_array_test(openram_test):
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# check write driver array for single port
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debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
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a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
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a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4, port=0)
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self.local_check(a)
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debug.info(2, "Testing write_mask_and_array for columns=16, word_size=16, write_size=4")
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=16, write_size=4)
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=16, write_size=4, port=0)
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self.local_check(a)
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debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2")
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2, port=0)
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self.local_check(a)
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# check write driver array for multi-port
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@ -43,11 +43,11 @@ class write_mask_and_array_test(openram_test):
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factory.reset()
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debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4 (multi-port case)")
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a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4)
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a = factory.create(module_type="write_mask_and_array", columns=8, word_size=8, write_size=4, port=0)
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self.local_check(a)
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debug.info(2, "Testing write_mask_and_array for columns=16, word_size=8, write_size=2 (multi-port case)")
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2)
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a = factory.create(module_type="write_mask_and_array", columns=16, word_size=8, write_size=2, port=0)
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self.local_check(a)
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globals.end_openram()
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