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OpenRAM
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Cleanup unit test. Fix s_en control bug for r-only.

This commit is contained in:
mrg 2019-07-16 13:51:31 -07:00
parent 2f55911604
commit 12fa36317e
4 changed files with 10 additions and 12 deletions
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4
compiler/modules/bank.py
View File

@ -79,9 +79,9 @@ class bank(design.design):
for bit in range(self.word_size):
self.add_pin("dout{0}_{1}".format(port,bit),"OUT")
for port in self.read_ports:
self.add_pin(self.bitcell_array.get_rbl_bl_name(port),"OUT")
self.add_pin(self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]),"OUT")
for port in self.read_ports:
self.add_pin(self.bitcell_array.get_rbl_wl_name(port),"IN")
self.add_pin(self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port]),"IN")
for port in self.write_ports:
for bit in range(self.word_size):
self.add_pin("din{0}_{1}".format(port,bit),"IN")

1
compiler/modules/control_logic.py
View File

@ -422,6 +422,7 @@ class control_logic(design.design):
if (self.port_type == "rw") or (self.port_type == "r") or self.words_per_row>1:
self.place_pen_row(row)
row += 1
if (self.port_type == "rw") or (self.port_type == "r"):
self.place_sen_row(row)
row += 1
self.place_delay(row)

16
compiler/tests/19_psingle_bank_test.py
View File

@ -20,16 +20,16 @@ class psingle_bank_test(openram_test):
def runTest(self):
globals.init_openram("config_{0}".format(OPTS.tech_name))
from bank import bank
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
OPTS.dummy_bitcell="dummy_pbitcell"
# testing layout of bank using pbitcell with 1 RW port (a 6T-cell equivalent)
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
c = sram_config(word_size=4,
num_words=16)
@ -37,8 +37,7 @@ class psingle_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=32
@ -46,8 +45,7 @@ class psingle_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.num_words=64
@ -55,8 +53,7 @@ class psingle_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
c.word_size=2
@ -65,8 +62,7 @@ class psingle_bank_test(openram_test):
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
a = bank(c, name=name)
a = factory.create(module_type="bank", sram_config=c)
self.local_check(a)
globals.end_openram()

1
compiler/tests/19_single_bank_1w_1r_test.py
View File

@ -24,6 +24,7 @@ class single_bank_1w_1r_test(openram_test):
OPTS.bitcell = "bitcell_1w_1r"
OPTS.replica_bitcell = "replica_bitcell_1w_1r"
OPTS.dummy_bitcell="dummy_bitcell_1w_1r"
OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1
OPTS.num_w_ports = 1