mirror of https://github.com/VLSIDA/OpenRAM.git
Undo changes for config expansion. Change unit tests to use OPENRAM_HOME.
This commit is contained in:
Matthew Guthaus
parent
7e9d08206c
commit
c4cf8134fe
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@ -167,7 +167,7 @@ class instance(geometry):
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debug.info(4, "creating instance: " + self.name)
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def get_blockages(self, layer, top=False):
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def get_blockages(self, lpp, top=False):
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""" Retrieve blockages of all modules in this instance.
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Apply the transform of the instance placement to give absolute blockages."""
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angle = math.radians(float(self.rotate))
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@ -191,11 +191,11 @@ class instance(geometry):
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if self.mod.is_library_cell:
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# Writes library cell blockages as shapes instead of a large metal blockage
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blockages = []
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blockages = self.mod.gds.getBlockages(layer)
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blockages = self.mod.gds.getBlockages(lpp)
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for b in blockages:
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new_blockages.append(self.transform_coords(b,self.offset, mirr, angle))
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else:
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blockages = self.mod.get_blockages(layer)
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blockages = self.mod.get_blockages(lpp)
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for b in blockages:
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new_blockages.append(self.transform_coords(b,self.offset, mirr, angle))
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return new_blockages
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@ -539,21 +539,21 @@ class layout():
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Do not write the pins since they aren't obstructions.
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"""
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if type(layer)==str:
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layer_num = techlayer[layer][0]
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lpp = techlayer[layer]
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else:
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layer_num = layer
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lpp = layer
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blockages = []
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for i in self.objs:
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blockages += i.get_blockages(layer_num)
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blockages += i.get_blockages(lpp)
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for i in self.insts:
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blockages += i.get_blockages(layer_num)
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blockages += i.get_blockages(lpp)
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# Must add pin blockages to non-top cells
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if not top_level:
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blockages += self.get_pin_blockages(layer_num)
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blockages += self.get_pin_blockages(lpp)
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return blockages
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def get_pin_blockages(self, layer_num):
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def get_pin_blockages(self, lpp):
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""" Return the pin shapes as blockages for non-top-level blocks. """
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# FIXME: We don't have a body contact in ptx, so just ignore it for now
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import copy
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@ -565,33 +565,57 @@ class layout():
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for pin_name in pin_names:
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pin_list = self.get_pins(pin_name)
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for pin in pin_list:
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if pin.layer_num==layer_num:
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if pin.same_lpp(pin.lpp, lpp):
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blockages += [pin.rect]
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return blockages
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def create_horizontal_pin_bus(self, layer, pitch, offset, names, length):
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""" Create a horizontal bus of pins. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=True)
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return self.create_bus(layer,
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pitch,
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offset,
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names,
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length,
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vertical=False,
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make_pins=True)
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def create_vertical_pin_bus(self, layer, pitch, offset, names, length):
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""" Create a horizontal bus of pins. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=True)
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return self.create_bus(layer,
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pitch,
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offset,
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names,
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length,
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vertical=True,
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make_pins=True)
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def create_vertical_bus(self, layer, pitch, offset, names, length):
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""" Create a horizontal bus. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=True,make_pins=False)
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return self.create_bus(layer,
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pitch,
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offset,
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names,
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length,
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vertical=True,
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make_pins=False)
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def create_horizontal_bus(self, layer, pitch, offset, names, length):
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""" Create a horizontal bus. """
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return self.create_bus(layer,pitch,offset,names,length,vertical=False,make_pins=False)
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return self.create_bus(layer,
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pitch,
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offset,
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names,
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length,
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vertical=False,
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make_pins=False)
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def create_bus(self, layer, pitch, offset, names, length, vertical, make_pins):
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"""
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"""
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Create a horizontal or vertical bus. It can be either just rectangles, or actual
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layout pins. It returns an map of line center line positions indexed by name.
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The other coordinate is a 0 since the bus provides a range.
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The other coordinate is a 0 since the bus provides a range.
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TODO: combine with channel router.
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"""
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@ -282,13 +282,9 @@ def read_config(config_file, is_unit_test=True):
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# it is already not an abs path, make it one
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if not os.path.isabs(config_file):
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try:
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OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
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except:
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debug.error("$OPENRAM_HOME is not properly defined.", 1)
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config_file = OPENRAM_HOME + "/tests/" + config_file + ".py"
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debug.check(os.path.isfile(config_file),
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"{} is not a valid config file".format(config_file))
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config_file = os.getcwd() + "/" + config_file
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# Make it a python file if the base name was only given
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config_file = re.sub(r'\.py$', "", config_file)
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# Expand the user if it is used
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@ -297,16 +293,14 @@ def read_config(config_file, is_unit_test=True):
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# Add the path to the system path
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# so we can import things in the other directory
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dir_name = os.path.dirname(config_file)
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file_name = os.path.basename(config_file)
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# Remove the py from the module name
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file_name = re.sub(r'\.py$', "", file_name)
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module_name = os.path.basename(config_file)
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# Prepend the path to avoid if we are using the example config
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sys.path.insert(0, dir_name)
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# Import the configuration file of which modules to use
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debug.info(1, "Configuration file is " + config_file + ".py")
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try:
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config = importlib.import_module(file_name)
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config = importlib.import_module(module_name)
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except:
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debug.error("Unable to read configuration file: {0}".format(config_file),2)
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@ -315,7 +309,7 @@ def read_config(config_file, is_unit_test=True):
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# except in the case of the tech name! This is because the tech name
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# is sometimes used to specify the config file itself (e.g. unit tests)
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# Note that if we re-read a config file, nothing will get read again!
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if not k in OPTS.__dict__ or k == "tech_name":
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if k not in OPTS.__dict__ or k == "tech_name":
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OPTS.__dict__[k] = v
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# Massage the output path to be an absolute one
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@ -17,7 +17,8 @@ import debug
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class library_drc_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import verify
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(gds_dir, gds_files) = setup_files()
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@ -17,7 +17,8 @@ import debug
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class library_lvs_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import verify
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(gds_dir, sp_dir, allnames) = setup_files()
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@ -18,7 +18,8 @@ import debug
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class contact_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]:
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stack_name = ":".join(map(str, layer_stack))
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@ -17,7 +17,8 @@ import debug
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class path_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import wire_path
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import tech
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import design
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@ -18,7 +18,8 @@ import debug
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class ptx_1finger_nmos_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking min size NMOS with 1 finger")
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@ -18,7 +18,8 @@ import debug
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class ptx_1finger_pmos_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking min size PMOS with 1 finger")
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@ -18,7 +18,8 @@ import debug
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class ptx_3finger_nmos_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking three fingers NMOS")
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@ -18,7 +18,8 @@ import debug
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class ptx_3finger_pmos_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking three fingers PMOS")
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@ -18,7 +18,8 @@ import debug
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class ptx_4finger_nmos_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking three fingers NMOS")
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@ -18,7 +18,8 @@ import debug
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class ptx_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import tech
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debug.info(2, "Checking three fingers PMOS")
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@ -17,7 +17,8 @@ import debug
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class wire_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import wire
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import tech
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import design
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@ -18,7 +18,8 @@ import debug
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class replica_pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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import dummy_pbitcell
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OPTS.bitcell = "pbitcell"
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@ -18,7 +18,8 @@ import debug
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class pand2_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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global verify
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import verify
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@ -18,7 +18,8 @@ import debug
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class pand3_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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global verify
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import verify
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@ -19,7 +19,8 @@ from sram_factory import factory
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class pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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@ -18,7 +18,8 @@ import debug
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class pbuf_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Testing inverter/buffer 4x 8x")
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a = factory.create(module_type="pbuf", size=8)
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@ -18,7 +18,8 @@ import debug
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class pdriver_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Testing inverter/buffer 4x 8x")
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# a tests the error message for specifying conflicting conditions
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@ -18,7 +18,8 @@ import debug
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class pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Checking 8x inverter")
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tx = factory.create(module_type="pinv", size=8)
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@ -18,7 +18,8 @@ import debug
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class pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Checking 1x beta=3 size inverter")
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tx = factory.create(module_type="pinv", size=1, beta=3)
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@ -18,7 +18,8 @@ import debug
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class pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Checking 1x size inverter")
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tx = factory.create(module_type="pinv", size=1)
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@ -18,7 +18,8 @@ import debug
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class pinv_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Checking 2x size inverter")
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tx = factory.create(module_type="pinv", size=2)
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@ -18,7 +18,8 @@ import debug
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class pinvbuf_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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debug.info(2, "Testing inverter/buffer 4x 8x")
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a = factory.create(module_type="pinvbuf", size=8)
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@ -18,7 +18,8 @@ import debug
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class pnand2_test(openram_test):
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def runTest(self):
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globals.init_openram("{}/config".format(OPTS.tech_name))
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config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
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globals.init_openram(config_file)
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|
||||
debug.info(2, "Checking 2-input nand gate")
|
||||
tx = factory.create(module_type="pnand2", size=1)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class pnand3_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Checking 3-input nand gate")
|
||||
tx = factory.create(module_type="pnand3", size=1)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class pnor2_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Checking 2-input nor gate")
|
||||
tx = factory.create(module_type="pnor2", size=1)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class precharge_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check precharge in single port
|
||||
debug.info(2, "Checking precharge for handmade bitcell")
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class replica_pbitcell_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
import replica_pbitcell
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ import debug
|
|||
class single_level_column_mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check single level column mux in single port
|
||||
debug.info(2, "Checking column mux")
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@ import debug
|
|||
class bitcell_1rw_1r_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ import debug
|
|||
class array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing 4x4 array for 6t_cell")
|
||||
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class dummy_row_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing dummy row for 6t_cell")
|
||||
a = factory.create(module_type="dummy_array", rows=1, cols=4)
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class pbitcell_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class replica_bitcell_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell = "replica_pbitcell"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class hierarchical_decoder_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
# Doesn't require hierarchical decoder
|
||||
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
|
||||
# a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class hierarchical_predecode2x4_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# checking hierarchical precode 2x4 for single port
|
||||
debug.info(1, "Testing sample for hierarchy_predecode2x4")
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class hierarchical_predecode3x8_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# checking hierarchical precode 3x8 for single port
|
||||
debug.info(1, "Testing sample for hierarchy_predecode3x8")
|
||||
|
|
|
|||
|
|
@ -17,7 +17,8 @@ import debug
|
|||
class single_level_column_mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
import single_level_column_mux_array
|
||||
|
||||
# check single level column mux array in single port
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class precharge_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check precharge array in single port
|
||||
debug.info(2, "Checking 3 column precharge")
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ import debug
|
|||
class wordline_driver_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check wordline driver for single port
|
||||
debug.info(2, "Checking driver")
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class sense_amp_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check sense amp array for single port
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class write_driver_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check write driver array for single port
|
||||
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ import debug
|
|||
class write_driver_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check write driver array for single port
|
||||
debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
|
||||
|
|
@ -58,4 +59,4 @@ if __name__ == "__main__":
|
|||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ import debug
|
|||
class write_mask_and_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
# check write driver array for single port
|
||||
debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class dff_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing dff_array for 3x3")
|
||||
a = factory.create(module_type="dff_array", rows=3, columns=3)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class dff_buf_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing dff_buf_array for 3x3")
|
||||
a = factory.create(module_type="dff_buf_array", rows=3, columns=3)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class dff_buf_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing dff_buf 4x 8x")
|
||||
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class tri_gate_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
|
||||
a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class delay_chain_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing delay_chain")
|
||||
a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class replica_bitcell_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class replica_bitcell_array_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing 4x4 array for 6t_cell")
|
||||
a = factory.create(module_type="replica_bitcell_array", cols=4, rows=4, left_rbl=1, right_rbl=0, bitcell_ports=[0])
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class replica_column_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(2, "Testing replica column for 6t_cell")
|
||||
a = factory.create(module_type="replica_column", rows=4, left_rbl=1, right_rbl=0, replica_bit=1)
|
||||
|
|
|
|||
|
|
@ -22,7 +22,8 @@ import debug
|
|||
class control_logic_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
import control_logic
|
||||
import tech
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class control_logic_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
import control_logic
|
||||
import tech
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class port_address_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(1, "Port address 16 rows")
|
||||
a = factory.create("port_address", cols=16, rows=16)
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@ import debug
|
|||
class port_data_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
c = sram_config(word_size=4,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class port_data_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
c = sram_config(word_size=16,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class bank_select_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
|
||||
debug.info(1, "No column mux, rw control logic")
|
||||
a = factory.create(module_type="bank_select", port="rw")
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class multi_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
c = sram_config(word_size=4,
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class multi_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class psingle_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class single_bank_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class single_bank_1w_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1w_1r"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class single_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
c = sram_config(word_size=4,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class single_bank_wmask_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -18,8 +18,9 @@ import debug
|
|||
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
|
||||
class psram_1bank_2mux_1rw_1w_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ import debug
|
|||
class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
@ -58,4 +59,4 @@ if __name__ == "__main__":
|
|||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
|
|||
|
|
@ -18,8 +18,9 @@ import debug
|
|||
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
|
||||
class psram_1bank_2mux_1w_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -18,8 +18,9 @@ import debug
|
|||
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
|
||||
class psram_1bank_2mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
OPTS.bitcell = "pbitcell"
|
||||
OPTS.replica_bitcell="replica_pbitcell"
|
||||
|
|
|
|||
|
|
@ -17,8 +17,9 @@ import debug
|
|||
|
||||
class psram_1bank_4mux_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "pbitcell"
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class sram_1bank_2mux_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -18,8 +18,9 @@ import debug
|
|||
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
|
||||
class psram_1bank_2mux_1w_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
def runTest(self):
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1w_1r"
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_2mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=32,
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ import debug
|
|||
class sram_1bank_2mux_wmask_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=8,
|
||||
write_size=4,
|
||||
|
|
@ -51,4 +52,4 @@ if __name__ == "__main__":
|
|||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ import debug
|
|||
class sram_1bank_32b_1024_wmask_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=32,
|
||||
write_size=8,
|
||||
|
|
@ -50,4 +51,4 @@ if __name__ == "__main__":
|
|||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_4mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=64,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class sram_1bank_8mux_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_8mux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=2,
|
||||
num_words=128,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class sram_1bank_nomux_1rw_1r_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
|
||||
OPTS.bitcell = "bitcell_1rw_1r"
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_nomux_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=4,
|
||||
num_words=16,
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ import debug
|
|||
class sram_1bank_nomux_wmask_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=8,
|
||||
write_size=4,
|
||||
|
|
@ -51,4 +52,4 @@ if __name__ == "__main__":
|
|||
(OPTS, args) = globals.parse_args()
|
||||
del sys.argv[1:]
|
||||
header(__file__, OPTS.tech_name)
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
unittest.main(testRunner=debugTestRunner())
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_2bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
from sram_config import sram_config
|
||||
c = sram_config(word_size=16,
|
||||
num_words=32,
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class timing_sram_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.spice_name="hspice"
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class timing_setup_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.spice_name="hspice"
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
|
|
|||
|
|
@ -20,7 +20,8 @@ class model_delay_test(openram_test):
|
|||
""" Compare the accuracy of the analytical model with a spice simulation. """
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class timing_sram_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.spice_name="ngspice"
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class timing_setup_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.spice_name="ngspice"
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
|
|
|||
|
|
@ -18,7 +18,8 @@ import debug
|
|||
class psram_1bank_2mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class psram_1bank_4mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class psram_1bank_8mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class psram_1bank_nomux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_2mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_4mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_8mux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_1bank_nomux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class psram_1bank_nomux_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -21,7 +21,8 @@ import debug
|
|||
class sram_wmask_1w_1r_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
|
|
@ -19,7 +19,8 @@ import debug
|
|||
class sram_wmask_func_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("{}/config".format(OPTS.tech_name))
|
||||
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
|
||||
globals.init_openram(config_file)
|
||||
OPTS.analytical_delay = False
|
||||
OPTS.netlist_only = True
|
||||
OPTS.trim_netlist = False
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue