mirror of https://github.com/VLSIDA/OpenRAM.git
Remove old replica bitline.
This commit is contained in:
Matt Guthaus
parent
a707c6fa50
commit
864639d96e
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@ -1,270 +0,0 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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from tech import drc
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import contact
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class replica_bitline(design.design):
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"""
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Generate a module that simulates the delay of control logic
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and bit line charging. Stages is the depth of the delay
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line and rows is the height of the replica bit loads.
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"""
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def __init__(self, name, delay_fanout_list, bitcell_loads):
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design.design.__init__(self, name)
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self.bitcell_loads = bitcell_loads
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self.delay_fanout_list = delay_fanout_list
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if len(delay_fanout_list) == 0 or len(delay_fanout_list)%2 == 1:
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debug.error('Delay chain must contain an even amount of stages to maintain polarity.',1)
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.calculate_module_offsets()
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self.place_instances()
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self.route()
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self.add_layout_pins()
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self.offset_all_coordinates()
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#self.add_lvs_correspondence_points()
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# Extra pitch on top and right
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self.width = self.delay_chain_inst.rx() + self.m2_pitch
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self.height = self.delay_chain_inst.uy() + self.m3_pitch
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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pin_list = ["en", "bl", "wl", "out", "vdd", "gnd"]
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pin_dir = ["INPUT", "INPUT", "OUTPUT", "OUTPUT", "POWER", "GROUND"]
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self.add_pin_list(pin_list, pin_dir)
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def calculate_module_offsets(self):
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""" Calculate all the module offsets """
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# Quadrant 4: with some space below it and tracks on the right for vdd/gnd
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self.delay_chain_offset = vector(0, self.inv.height)
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# Will be flipped vertically below the delay chain
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# Align it with the inverters in the delay chain to simplify supply connections
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self.rbl_inv_offset = self.delay_chain_offset + vector(2*self.inv.width, 0)
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# Placed next to the replica bitcell
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self.access_tx_offset = vector(self.rbl_inv_offset.x + self.inv.width, 0.5*self.inv.height)
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def add_modules(self):
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""" Add the modules for later usage """
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# FIXME: The FO and depth of this should be tuned
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self.delay_chain = factory.create(module_type="delay_chain",
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fanout_list=self.delay_fanout_list)
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self.add_mod(self.delay_chain)
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self.inv = factory.create(module_type="pinv")
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self.add_mod(self.inv)
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self.access_tx = factory.create(module_type="ptx",
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tx_type="pmos")
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self.add_mod(self.access_tx)
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def create_instances(self):
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""" Create all of the module instances in the logical netlist """
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# This is the threshold detect inverter on the output of the RBL
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self.rbl_inv_inst=self.add_inst(name="rbl_inv",
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mod=self.inv)
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self.connect_inst(["bl0_0", "out", "vdd", "gnd"])
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self.tx_inst=self.add_inst(name="rbl_access_tx",
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mod=self.access_tx)
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# D, G, S, B
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self.connect_inst(["vdd", "delayed_en", "bl0_0", "vdd"])
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# add the well and poly contact
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self.delay_chain_inst=self.add_inst(name="delay_chain",
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mod=self.delay_chain)
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self.connect_inst(["en", "delayed_en", "vdd", "gnd"])
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def place_instances(self):
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""" Add all of the module instances in the logical netlist """
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# This is the threshold detect inverter on the output of the RBL
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self.rbl_inv_inst.place(offset=self.rbl_inv_offset,
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rotate=180)
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self.tx_inst.place(self.access_tx_offset)
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self.delay_chain_inst.place(self.delay_chain_offset)
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def route(self):
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""" Connect all the signals together """
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self.route_supplies()
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self.route_access_tx()
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def route_supplies(self):
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""" Propagate all vdd/gnd pins up to this level for all modules """
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self.copy_layout_pin(self.delay_chain_inst, "vdd")
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self.copy_layout_pin(self.delay_chain_inst, "gnd")
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# Route the inverter supply pin from M1
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# Only vdd is needed because gnd shares a rail with the delay chain
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pin = self.rbl_inv_inst.get_pin("vdd")
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self.add_power_pin("vdd", pin.lc())
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def route_access_tx(self):
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# GATE ROUTE
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# 1. Add the poly contact and nwell enclosure
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# Determines the y-coordinate of where to place the gate input poly pin
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# (middle in between the pmos and nmos)
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poly_pin = self.tx_inst.get_pin("G")
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poly_offset = poly_pin.uc()
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# This centers the contact above the poly by one pitch
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contact_offset = poly_offset + vector(0,self.m2_pitch)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=contact_offset)
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=contact_offset)
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self.add_segment_center(layer="poly",
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start=poly_offset,
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end=contact_offset)
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nwell_offset = self.rbl_inv_offset + vector(-self.inv.height,self.inv.width)
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# self.add_rect(layer="nwell",
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# offset=nwell_offset,
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# width=0.5*self.inv.height,
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# height=self.delay_chain_offset.y-nwell_offset.y)
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# 2. Route delay chain output to access tx gate
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delay_en_offset = self.delay_chain_inst.get_pin("out").bc()
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self.add_path("metal2", [delay_en_offset,contact_offset])
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# 3. Route the contact of previous route to the bitcell WL
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# route bend of previous net to bitcell WL
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self.add_layout_pin_rect_center(text="wl",
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layer="metal1",
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offset=contact_offset)
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# DRAIN ROUTE
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# Route the drain to the vdd rail
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drain_offset = self.tx_inst.get_pin("D").center()
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self.add_power_pin("vdd", drain_offset, vertical=True)
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# SOURCE ROUTE
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# Route the drain to the RBL inverter input
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source_offset = self.tx_inst.get_pin("S").center()
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inv_A_offset = self.rbl_inv_inst.get_pin("A").center()
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self.add_path("metal1",[source_offset, inv_A_offset])
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# Route the connection of the source route to the RBL bitline (left)
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source_down_offset = source_offset - vector(0,3*self.m2_pitch)
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self.add_path("metal1",[source_offset, source_down_offset])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=source_offset)
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self.add_layout_pin_rect_center(text="bl",
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layer="metal1",
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offset=source_down_offset)
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# BODY ROUTE
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# Connect it to the inverter well
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nwell_offset = self.rbl_inv_inst.lr()
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ur_offset = self.tx_inst.ur()
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self.add_rect(layer="nwell",
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offset=nwell_offset,
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width=ur_offset.x-nwell_offset.x,
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height=ur_offset.y-nwell_offset.y)
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def add_layout_pins(self):
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""" Route the input and output signal """
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en_offset = self.delay_chain_inst.get_pin("in").bc()
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self.add_layout_pin_segment_center(text="en",
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layer="metal2",
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start=en_offset,
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end=en_offset.scale(1,0))
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out_offset = self.rbl_inv_inst.get_pin("Z").center()
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self.add_layout_pin_segment_center(text="out",
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layer="metal2",
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start=out_offset,
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end=out_offset.scale(1,0))
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=out_offset)
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def add_lvs_correspondence_points(self):
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""" This adds some points for easier debugging if LVS goes wrong.
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These should probably be turned off by default though, since extraction
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will show these as ports in the extracted netlist.
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"""
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pin = self.rbl_inv_inst.get_pin("A")
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self.add_label_pin(text="bl[0]",
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layer=pin.layer,
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offset=pin.ll(),
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height=pin.height(),
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width=pin.width())
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pin = self.delay_chain_inst.get_pin("out")
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self.add_label_pin(text="delayed_en",
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layer=pin.layer,
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offset=pin.ll(),
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height=pin.height(),
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width=pin.width())
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def get_en_cin(self):
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"""Get the enable input relative capacitance"""
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#The enable is only connected to the delay, get the cin from that module
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en_cin = self.delay_chain.get_cin()
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return en_cin
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def determine_sen_stage_efforts(self, ext_cout, inp_is_rise=True):
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"""Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load."""
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stage_effort_list = []
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#Stage 1 is the delay chain
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stage1_cout = self.get_delayed_en_cin()
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stage1 = self.delay_chain.determine_delayed_en_stage_efforts(stage1_cout, inp_is_rise)
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stage_effort_list += stage1
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#There is a disconnect between the delay chain and inverter. The rise/fall of the input to the inverter
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#Will be the negation of the previous stage.
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last_stage_is_rise = not stage_effort_list[-1].is_rise
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#The delay chain triggers the enable on the replica bitline (rbl). This is used to track the bitline delay whereas this
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#model is intended to track every but that. Therefore, the next stage is the inverter after the rbl.
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stage2 = self.inv.get_stage_effort(ext_cout, last_stage_is_rise)
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stage_effort_list.append(stage2)
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return stage_effort_list
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def get_delayed_en_cin(self):
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"""Get the fanout capacitance (relative) of the delayed enable from the delay chain."""
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access_tx_cin = self.access_tx.get_cin()
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rbc_cin = self.replica_bitcell.get_wl_cin()
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return access_tx_cin + rbc_cin
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@ -1,68 +0,0 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys,os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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class replica_bitline_multiport_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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stages=4
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fanout=4
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rows=13
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OPTS.bitcell = "bitcell_1rw_1r"
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OPTS.replica_bitcell = "replica_bitcell_1rw_1r"
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OPTS.dummy_bitcell = "dummy_bitcell_1rw_1r"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 0
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factory.reset()
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debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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# check replica bitline in pbitcell multi-port
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell = "replica_pbitcell"
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OPTS.dummy_bitcell = "dummy_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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factory.reset()
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debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 1
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OPTS.num_r_ports = 1
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factory.reset()
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debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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@ -1,44 +0,0 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys,os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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class replica_bitline_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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# check replica bitline in single port
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stages=4
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fanout=4
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rows=13
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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stages=8
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rows=100
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debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
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a = factory.create(module_type="replica_bitline", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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