mirror of https://github.com/VLSIDA/OpenRAM.git
Make wire test programmatic
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@ -22,107 +22,32 @@ class wire_test(openram_test):
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import wire
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import tech
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import design
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min_space = 2 * (tech.drc["minwidth_poly"] +
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tech.drc["minwidth_m1"])
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layer_stack = tech.poly_stack
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x-min_space, y-min_space] for x,y in old_position_list]
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w = design.design("wire_test1")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_poly"] +
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tech.drc["minwidth_m1"])
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layer_stack = tech.poly_stack
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old_position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x+min_space, y+min_space] for x,y in old_position_list]
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w = design.design("wire_test2")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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layer_stacks = [tech.poly_stack] + tech.beol_stacks
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min_space = 2 * (tech.drc["minwidth_m2"] +
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tech.drc["minwidth_m1"])
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layer_stack = tech.m1_stack
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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w = design.design("wire_test3")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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for reverse in [False, True]:
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for stack in layer_stacks:
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if reverse:
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layer_stack = stack[::-1]
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else:
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layer_stack = stack
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min_space = 2 * (tech.drc["minwidth_{}".format(layer_stack[0])] +
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tech.drc["minwidth_{}".format(layer_stack[2])])
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min_space = 2 * (tech.drc["minwidth_m2"] +
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tech.drc["minwidth_m1"])
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layer_stack = tech.m2_stack[::-1]
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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w = design.design("wire_test4")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_m2"] +
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tech.drc["minwidth_m3"])
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layer_stack = tech.m2_stack
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list.reverse()
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w = design.design("wire_test5")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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min_space = 2 * (tech.drc["minwidth_m2"] +
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tech.drc["minwidth_m3"])
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layer_stack = tech.m2_stack[::-1]
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list.reverse()
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w = design.design("wire_test6")
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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position_list = [[0, 0],
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[0, 3 * min_space],
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[1 * min_space, 3 * min_space],
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[4 * min_space, 3 * min_space],
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[4 * min_space, 0],
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[7 * min_space, 0],
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[7 * min_space, 4 * min_space],
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[-1 * min_space, 4 * min_space],
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[-1 * min_space, 0]]
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position_list = [[x - min_space, y - min_space] for x, y in position_list]
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w = design.design("wire_test_{}".format("_".join(layer_stack)))
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wire.wire(w, layer_stack, position_list)
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self.local_drc_check(w)
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globals.end_openram()
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