mirror of https://github.com/VLSIDA/OpenRAM.git
Placed wmask dff and added connections for wmask pins.
This commit is contained in:
jsowash
parent
0d7170eb95
commit
858fbb062d
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@ -121,7 +121,7 @@ class bank(design.design):
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self.route_column_address_lines(port)
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self.route_control_lines(port)
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if self.num_banks > 1:
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self.route_bank_select(port)
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self.route_bank_select(port)
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self.route_supplies()
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@ -700,6 +700,15 @@ class bank(design.design):
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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#
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# if self.word_size is not None:
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# for bit in range(self.num_wmasks):
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# wmask_pin = self.port_data_inst[port].get_pin("bank_wmask_{0}".format(bit))
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# self.add_layout_pin_rect_center(text="bank_wmask{0}_{1}".format(port, bit),
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# layer=wmask_pin.layer,
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# offset=wmask_pin.center(),
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# height=wmask_pin.height(),
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# width=wmask_pin.width())
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def route_port_address_in(self, port):
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@ -711,8 +720,9 @@ class bank(design.design):
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decoder_name = "addr_{}".format(row)
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addr_name = "addr{0}_{1}".format(port,addr_idx)
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self.copy_layout_pin(self.port_address_inst[port], decoder_name, addr_name)
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def route_port_data_in(self, port):
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""" Connecting port data in """
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@ -720,6 +730,14 @@ class bank(design.design):
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data_name = "din_{}".format(row)
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din_name = "din{0}_{1}".format(port,row)
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self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
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if self.word_size is not None:
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for row in range(self.num_wmasks):
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wmask_name = "bank_wmask_{}".format(row)
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bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)
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self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name)
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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inst1_bl_name="bl_{}", inst1_br_name="br_{}",
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@ -86,9 +86,19 @@ class sram_1bank(sram_base):
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data_pos[port] = vector(self.bank.bank_array_ll.x,
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-max_gap_size - self.dff.height)
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self.data_dff_insts[port].place(data_pos[port])
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else:
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data_pos[port] = vector(self.bank.bank_array_ll.x,0)
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# Add the write mask flops below the din flops.
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if self.write_size is not None:
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if port in self.write_ports:
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wmask_pos[port] = vector(self.bank.bank_array_ll.x,
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- 2*max_gap_size - 2*self.dff.height)
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self.wmask_dff_insts[port].place(wmask_pos[port])
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else:
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wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
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# Add the col address flops below the bank to the left of the lower-left of bank array
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if self.col_addr_dff:
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col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap,
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@ -125,14 +135,14 @@ class sram_1bank(sram_base):
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-max_gap_size - self.data_dff_insts[port].height)
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self.data_dff_insts[port].place(data_pos[port])
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# Add the write mask flops below the din flops.
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if self.write_size is not None:
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if port in self.write_ports:
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wmask_pos[port] = vector(self.bank.bank_array_ll.x,
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-max_gap_size - self.wmask_dff_insts[port].height)
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# wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
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# -max_gap_size - self.wmask_dff_insts[port].height)
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self.wmask_dff_insts[port].place(wmask_pos[port])
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# # Add the write mask flops below the din flops.
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# if self.write_size is not None:
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# if port in self.write_ports:
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# wmask_pos[port] = vector(self.bank.bank_array_ll.x,
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# -max_gap_size - self.wmask_dff_insts[port].height)
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# # wmask_pos[port] = vector(self.bank.bank_array_ll.x - self.control_logic_insts[port].width,
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# # -max_gap_size - self.wmask_dff_insts[port].height)
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# self.wmask_dff_insts[port].place(wmask_pos[port])
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if len(self.all_ports)>1:
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@ -149,6 +159,13 @@ class sram_1bank(sram_base):
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self.bank.height + max_gap_size + self.dff.height)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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# Add the write mask flops below the din flops.
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if self.write_size is not None:
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if port in self.write_ports:
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wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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self.bank.height + 2*max_gap_size + 2*self.dff.height)
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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# Add the write mask flops to the left of the din flops.
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if self.write_size is not None:
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if port in self.write_ports:
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@ -191,13 +208,13 @@ class sram_1bank(sram_base):
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self.bank.height + max_gap_size + self.dff.height)
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self.data_dff_insts[port].place(data_pos[port], mirror="MX")
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# Add the write mask flops to the left of the din flops.
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if self.write_size is not None:
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if port in self.write_ports:
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wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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self.bank.height + max_gap_size + self.data_dff_insts[port].height)
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self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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# # Add the write mask flops to the left of the din flops.
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# if self.write_size is not None:
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# if port in self.write_ports:
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# wmask_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
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# self.bank.height + max_gap_size + self.data_dff_insts[port].height)
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# self.wmask_dff_insts[port].place(wmask_pos[port], mirror="MX")
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#
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def add_layout_pins(self):
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"""
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@ -222,6 +239,10 @@ class sram_1bank(sram_base):
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if port in self.write_ports:
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for bit in range(self.word_size):
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self.copy_layout_pin(self.data_dff_insts[port], "din_{}".format(bit), "DIN{0}[{1}]".format(port,bit))
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if self.write_size is not None:
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for bit in range(self.num_wmasks):
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self.copy_layout_pin(self.wmask_dff_insts[port], "din_{}".format(bit), "wmask{0}[{1}]".format(port,bit))
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def route_layout(self):
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""" Route a single bank SRAM """
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@ -238,6 +259,7 @@ class sram_1bank(sram_base):
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self.route_col_addr_dff()
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self.route_data_dff()
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self.route_wmask_dff()
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def route_clk(self):
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""" Route the clock network """
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@ -290,6 +312,15 @@ class sram_1bank(sram_base):
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self.add_path("metal2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height))
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self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos])
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if self.write_size is not None:
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wmask_dff_clk_pin = self.wmask_dff_insts[port].get_pin("clk")
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wmask_dff_clk_pos = wmask_dff_clk_pin.center()
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mid_pos = vector(clk_steiner_pos.x, wmask_dff_clk_pos.y)
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# In some designs, the steiner via will be too close to the mid_pos via
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# so make the wire as wide as the contacts
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self.add_path("metal2", [mid_pos, clk_steiner_pos], width=max(m2m3.width, m2m3.height))
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self.add_wire(("metal3", "via2", "metal2"), [wmask_dff_clk_pos, mid_pos, clk_steiner_pos])
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def route_control_logic(self):
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""" Route the control logic pins that are not inputs """
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@ -367,7 +398,24 @@ class sram_1bank(sram_base):
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route_map = list(zip(bank_pins, dff_pins))
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self.create_horizontal_channel_route(route_map, offset)
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def route_wmask_dff(self):
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""" Connect the output of the wmask flops to the write mask AND array """
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# This is where the channel will start (y-dimension at least)
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for port in self.write_ports:
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if port % 2:
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offset = self.wmask_dff_insts[port].ll() - vector(0, (self.word_size + 2) * self.m1_pitch)
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else:
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offset = self.wmask_dff_insts[port].ul() + vector(0, 2 * self.m1_pitch)
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dff_names = ["dout_{}".format(x) for x in range(self.num_wmasks)]
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dff_pins = [self.wmask_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["bank_wmask{0}_{1}".format(port, x) for x in range(self.num_wmasks)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map = list(zip(bank_pins, dff_pins))
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self.create_horizontal_channel_route(route_map, offset)
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def add_lvs_correspondence_points(self):
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@ -0,0 +1,54 @@
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#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import unittest
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from testutils import *
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import sys, os
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sys.path.append(os.getenv("OPENRAM_HOME"))
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import globals
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from globals import OPTS
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from sram_factory import factory
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import debug
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# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test")
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class sram_1bank_nomux_wmask_test(openram_test):
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def runTest(self):
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globals.init_openram("config_{0}".format(OPTS.tech_name))
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from sram_config import sram_config
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c = sram_config(word_size=8,
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write_size=4,
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num_words=16,
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num_banks=1)
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c.words_per_row = 1
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c.recompute_sizes()
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debug.info(1, "Layout test for {}rw,{}r,{}w sram "
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"with {} bit words, {} words, {} bit writes, {} words per "
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"row, {} banks".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports,
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c.word_size,
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c.num_words,
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c.write_size,
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c.words_per_row,
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c.num_banks))
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a = factory.create(module_type="sram", sram_config=c)
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self.local_check(a, final_verification=True)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main(testRunner=debugTestRunner())
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