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OpenRAM
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Make unit test configs generic to tech_name

This commit is contained in:
Matthew Guthaus 2019-11-17 00:44:31 +00:00
parent b3b3cf0210
commit b3fb4e3183
114 changed files with 114 additions and 167 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/tests/01_library_drc_test.py
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@ -17,7 +17,7 @@ import debug
class library_drc_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import verify

2
compiler/tests/02_library_lvs_test.py
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@ -17,7 +17,7 @@ import debug
class library_lvs_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import verify

2
compiler/tests/03_contact_test.py
View File

@ -18,7 +18,7 @@ import debug
class contact_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
for layer_stack in [("metal1", "via1", "metal2"), ("poly", "contact", "metal1")]:

2
compiler/tests/03_path_test.py
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@ -17,7 +17,7 @@ import debug
class path_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import wire_path
import tech

2
compiler/tests/03_ptx_1finger_nmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_1finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_ptx_1finger_pmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_1finger_pmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_ptx_3finger_nmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_3finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_ptx_3finger_pmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_3finger_pmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_ptx_4finger_nmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_4finger_nmos_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_ptx_4finger_pmos_test.py
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@ -18,7 +18,7 @@ import debug
class ptx_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import tech

2
compiler/tests/03_wire_test.py
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@ -17,7 +17,7 @@ import debug
class wire_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import wire
import tech

2
compiler/tests/04_dummy_pbitcell_test.py
View File

@ -18,7 +18,7 @@ import debug
class replica_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import dummy_pbitcell

2
compiler/tests/04_pand2_test.py
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@ -18,7 +18,7 @@ import debug
class pand2_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify

2
compiler/tests/04_pand3_test.py
View File

@ -18,7 +18,7 @@ import debug
class pand3_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify

2
compiler/tests/04_pbitcell_test.py
View File

@ -19,7 +19,7 @@ from sram_factory import factory
class pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports=1

2
compiler/tests/04_pbuf_test.py
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@ -18,7 +18,7 @@ import debug
class pbuf_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing inverter/buffer 4x 8x")

2
compiler/tests/04_pdriver_test.py
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@ -18,7 +18,7 @@ import debug
class pdriver_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing inverter/buffer 4x 8x")

2
compiler/tests/04_pinv_10x_test.py
View File

@ -18,7 +18,7 @@ import debug
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 8x inverter")

2
compiler/tests/04_pinv_1x_beta_test.py
View File

@ -18,7 +18,7 @@ import debug
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 1x beta=3 size inverter")

2
compiler/tests/04_pinv_1x_test.py
View File

@ -18,7 +18,7 @@ import debug
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 1x size inverter")

2
compiler/tests/04_pinv_2x_test.py
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@ -18,7 +18,7 @@ import debug
class pinv_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 2x size inverter")

2
compiler/tests/04_pinvbuf_test.py
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@ -18,7 +18,7 @@ import debug
class pinvbuf_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing inverter/buffer 4x 8x")

2
compiler/tests/04_pnand2_test.py
View File

@ -18,7 +18,7 @@ import debug
class pnand2_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 2-input nand gate")

2
compiler/tests/04_pnand3_test.py
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@ -18,7 +18,7 @@ import debug
class pnand3_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 3-input nand gate")

2
compiler/tests/04_pnor2_test.py
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@ -18,7 +18,7 @@ import debug
class pnor2_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Checking 2-input nor gate")

2
compiler/tests/04_precharge_test.py
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@ -18,7 +18,7 @@ import debug
class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge in single port

2
compiler/tests/04_replica_pbitcell_test.py
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@ -18,7 +18,7 @@ import debug
class replica_pbitcell_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import replica_pbitcell

2
compiler/tests/04_single_level_column_mux_test.py
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@ -20,7 +20,7 @@ import debug
class single_level_column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check single level column mux in single port

2
compiler/tests/05_bitcell_1rw_1r_array_test.py
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@ -20,7 +20,7 @@ import debug
class bitcell_1rw_1r_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.bitcell = "bitcell_1rw_1r"

2
compiler/tests/05_bitcell_array_test.py
View File

@ -20,7 +20,7 @@ import debug
class array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing 4x4 array for 6t_cell")

2
compiler/tests/05_dummy_array_test.py
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@ -16,7 +16,7 @@ import debug
class dummy_row_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing dummy row for 6t_cell")

2
compiler/tests/05_pbitcell_array_test.py
View File

@ -19,7 +19,7 @@ import debug
class pbitcell_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")

2
compiler/tests/05_replica_pbitcell_array_test.py
View File

@ -16,7 +16,7 @@ import debug
class replica_bitcell_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.bitcell = "pbitcell"

2
compiler/tests/06_hierarchical_decoder_test.py
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@ -18,7 +18,7 @@ import debug
class hierarchical_decoder_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Doesn't require hierarchical decoder
# debug.info(1, "Testing 4 row sample for hierarchical_decoder")

2
compiler/tests/06_hierarchical_predecode2x4_test.py
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@ -18,7 +18,7 @@ import debug
class hierarchical_predecode2x4_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# checking hierarchical precode 2x4 for single port

2
compiler/tests/06_hierarchical_predecode3x8_test.py
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@ -18,7 +18,7 @@ import debug
class hierarchical_predecode3x8_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# checking hierarchical precode 3x8 for single port

2
compiler/tests/07_single_level_column_mux_array_test.py
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@ -17,7 +17,7 @@ import debug
class single_level_column_mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import single_level_column_mux_array

2
compiler/tests/08_precharge_array_test.py
View File

@ -18,7 +18,7 @@ import debug
class precharge_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in single port

2
compiler/tests/08_wordline_driver_test.py
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@ -20,7 +20,7 @@ import debug
class wordline_driver_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check wordline driver for single port

2
compiler/tests/09_sense_amp_array_test.py
View File

@ -18,7 +18,7 @@ import debug
class sense_amp_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check sense amp array for single port

2
compiler/tests/10_write_driver_array_test.py
View File

@ -18,7 +18,7 @@ import debug
class write_driver_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check write driver array for single port

2
compiler/tests/10_write_driver_array_wmask_test.py
View File

@ -20,7 +20,7 @@ import debug
class write_driver_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check write driver array for single port

2
compiler/tests/10_write_mask_and_array_test.py
View File

@ -20,7 +20,7 @@ import debug
class write_mask_and_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check write driver array for single port

2
compiler/tests/11_dff_array_test.py
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@ -18,7 +18,7 @@ import debug
class dff_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing dff_array for 3x3")

2
compiler/tests/11_dff_buf_array_test.py
View File

@ -18,7 +18,7 @@ import debug
class dff_buf_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing dff_buf_array for 3x3")

2
compiler/tests/11_dff_buf_test.py
View File

@ -18,7 +18,7 @@ import debug
class dff_buf_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing dff_buf 4x 8x")

2
compiler/tests/12_tri_gate_array_test.py
View File

@ -18,7 +18,7 @@ import debug
class tri_gate_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")

2
compiler/tests/13_delay_chain_test.py
View File

@ -18,7 +18,7 @@ import debug
class delay_chain_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing delay_chain")

2
compiler/tests/14_replica_bitcell_1rw_1r_array_test.py
View File

@ -16,7 +16,7 @@ import debug
class replica_bitcell_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.bitcell = "bitcell_1rw_1r"

2
compiler/tests/14_replica_bitcell_array_test.py
View File

@ -16,7 +16,7 @@ import debug
class replica_bitcell_array_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing 4x4 array for 6t_cell")

2
compiler/tests/14_replica_column_test.py
View File

@ -16,7 +16,7 @@ import debug
class replica_column_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(2, "Testing replica column for 6t_cell")

2
compiler/tests/16_control_logic_multiport_test.py
View File

@ -22,7 +22,7 @@ import debug
class control_logic_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import control_logic
import tech

2
compiler/tests/16_control_logic_test.py
View File

@ -18,7 +18,7 @@ import debug
class control_logic_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
import control_logic
import tech

2
compiler/tests/18_port_address_test.py
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@ -16,7 +16,7 @@ import debug
class port_address_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(1, "Port address 16 rows")

2
compiler/tests/18_port_data_test.py
View File

@ -16,7 +16,7 @@ import debug
class port_data_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/18_port_data_wmask_test.py
View File

@ -18,7 +18,7 @@ import debug
class port_data_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_bank_select_test.py
View File

@ -18,7 +18,7 @@ import debug
class bank_select_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
debug.info(1, "No column mux, rw control logic")

2
compiler/tests/19_multi_bank_test.py
View File

@ -19,7 +19,7 @@ import debug
class multi_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_pmulti_bank_test.py
View File

@ -19,7 +19,7 @@ import debug
class multi_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
OPTS.bitcell = "pbitcell"

2
compiler/tests/19_psingle_bank_test.py
View File

@ -19,7 +19,7 @@ import debug
class psingle_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_single_bank_1rw_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class single_bank_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_single_bank_1w_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class single_bank_1w_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_single_bank_test.py
View File

@ -18,7 +18,7 @@ import debug
class single_bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/19_single_bank_wmask_test.py
View File

@ -18,7 +18,7 @@ import debug
class single_bank_wmask_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
View File

@ -21,7 +21,7 @@ import debug
class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_psram_1bank_2mux_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_2mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
OPTS.bitcell = "pbitcell"

2
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class sram_1bank_2mux_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_sram_1bank_2mux_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_2mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=4,

2
compiler/tests/20_sram_1bank_2mux_wmask_test.py
View File

@ -21,7 +21,7 @@ import debug
class sram_1bank_2mux_wmask_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=8,

2
compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
View File

@ -21,7 +21,7 @@ import debug
class sram_1bank_32b_1024_wmask_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=32,

2
compiler/tests/20_sram_1bank_4mux_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_4mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=4,

2
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class sram_1bank_8mux_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_sram_1bank_8mux_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_8mux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=2,

2
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
View File

@ -18,7 +18,7 @@ import debug
class sram_1bank_nomux_1rw_1r_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config

2
compiler/tests/20_sram_1bank_nomux_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_nomux_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=4,

2
compiler/tests/20_sram_1bank_nomux_wmask_test.py
View File

@ -21,7 +21,7 @@ import debug
class sram_1bank_nomux_wmask_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=8,

2
compiler/tests/20_sram_2bank_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_2bank_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
c = sram_config(word_size=16,

2
compiler/tests/21_hspice_delay_test.py
View File

@ -18,7 +18,7 @@ import debug
class timing_sram_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name="hspice"
OPTS.analytical_delay = False

2
compiler/tests/21_hspice_setuphold_test.py
View File

@ -18,7 +18,7 @@ import debug
class timing_setup_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name="hspice"
OPTS.analytical_delay = False

2
compiler/tests/21_model_delay_test.py
View File

@ -20,7 +20,7 @@ class model_delay_test(openram_test):
""" Compare the accuracy of the analytical model with a spice simulation. """
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/21_ngspice_delay_test.py
View File

@ -18,7 +18,7 @@ import debug
class timing_sram_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False

2
compiler/tests/21_ngspice_setuphold_test.py
View File

@ -18,7 +18,7 @@ import debug
class timing_setup_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False

2
compiler/tests/22_psram_1bank_2mux_func_test.py
View File

@ -18,7 +18,7 @@ import debug
class psram_1bank_2mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_psram_1bank_4mux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_4mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_psram_1bank_8mux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_8mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_psram_1bank_nomux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_nomux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_1bank_2mux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_2mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_1bank_4mux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_4mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_1bank_8mux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_8mux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_1bank_nomux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_1bank_nomux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_1rw_1r_1bank_nomux_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class psram_1bank_nomux_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_wmask_1w_1r_func_test.py
View File

@ -21,7 +21,7 @@ import debug
class sram_wmask_1w_1r_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/22_sram_wmask_func_test.py
View File

@ -19,7 +19,7 @@ import debug
class sram_wmask_func_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True

2
compiler/tests/23_lib_sram_model_corners_test.py
View File

@ -18,7 +18,7 @@ import debug
class lib_model_corners_lib_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.netlist_only = True

2
compiler/tests/23_lib_sram_model_test.py
View File

@ -18,7 +18,7 @@ import debug
class lib_sram_model_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.netlist_only = True

2
compiler/tests/23_lib_sram_prune_test.py
View File

@ -18,7 +18,7 @@ import debug
class lib_sram_prune_test(openram_test):
def runTest(self):
config_file = "{}/tests/{}/config".format(os.getenv("OPENRAM_HOME"), OPTS.tech_name)
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.trim_netlist = True

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