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OpenRAM
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Additional debug. Smaller psram func tests.

This commit is contained in:
Matt Guthaus 2019-08-05 13:53:14 -07:00
parent e4532083da
commit 4d11de64ac
6 changed files with 24 additions and 19 deletions
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27
compiler/characterizer/simulation.py
View File

@ -25,9 +25,6 @@ class simulation():
self.word_size = self.sram.word_size
self.addr_size = self.sram.addr_size
self.write_size = self.sram.write_size
self.num_cols = self.sram.num_cols
self.num_rows = self.sram.num_rows
self.num_banks = self.sram.num_banks
self.sp_file = spfile
self.all_ports = self.sram.all_ports
@ -262,19 +259,21 @@ class simulation():
t_current+self.period)
elif op == "partial_write":
comment = "\tWriting (partial) {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)".format(word,
addr,
wmask,
port,
int(t_current / self.period),
t_current,
t_current + self.period)
addr,
wmask,
port,
int(t_current / self.period),
t_current,
t_current + self.period)
else:
comment = "\tReading {0} from address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
addr,
port,
int(t_current/self.period),
t_current,
t_current+self.period)
addr,
port,
int(t_current/self.period),
t_current,
t_current+self.period)
return comment
def gen_pin_names(self, port_signal_names, port_info, abits, dbits):

1
compiler/modules/control_logic.py
View File

@ -184,6 +184,7 @@ class control_logic(design.design):
# self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
# self.delay_chain_resized = True
debug.check(OPTS.delay_chain_stages%2, "Must use odd number of delay chain stages for inverting delay chain.")
self.delay_chain=factory.create(module_type="delay_chain",
fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage])
self.add_mod(self.delay_chain)

7
compiler/sram/sram_config.py
View File

@ -61,7 +61,6 @@ class sram_config:
self.tentative_num_rows = self.num_bits_per_bank / (self.words_per_row*self.word_size)
self.words_per_row = self.amend_words_per_row(self.tentative_num_rows, self.words_per_row)
debug.info(1,"Words per row: {}".format(self.words_per_row))
self.recompute_sizes()
def recompute_sizes(self):
@ -71,6 +70,8 @@ class sram_config:
SRAM for testing.
"""
debug.info(1,"Recomputing with words per row: {}".format(self.words_per_row))
# If the banks changed
self.num_words_per_bank = self.num_words/self.num_banks
self.num_bits_per_bank = self.word_size*self.num_words_per_bank
@ -78,12 +79,16 @@ class sram_config:
# Fix the number of columns and rows
self.num_cols = int(self.words_per_row*self.word_size)
self.num_rows = int(self.num_words_per_bank/self.words_per_row)
debug.info(1,"Rows: {} Cols: {}".format(self.num_rows,self.num_cols))
# Compute the address and bank sizes
self.row_addr_size = int(log(self.num_rows, 2))
self.col_addr_size = int(log(self.words_per_row, 2))
self.bank_addr_size = self.col_addr_size + self.row_addr_size
self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
debug.info(1,"Row addr size: {}".format(self.row_addr_size)
+ " Col addr size: {}".format(self.col_addr_size)
+ " Bank addr size: {}".format(self.bank_addr_size))
def estimate_words_per_row(self,tentative_num_cols, word_size):

4
compiler/tests/22_psram_1bank_2mux_func_test.py
View File

@ -37,8 +37,8 @@ class psram_1bank_2mux_func_test(openram_test):
reload(characterizer)
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=64,
c = sram_config(word_size=2,
num_words=32,
num_banks=1)
c.words_per_row=2
c.recompute_sizes()

2
compiler/tests/22_psram_1bank_4mux_func_test.py
View File

@ -38,7 +38,7 @@ class psram_1bank_4mux_func_test(openram_test):
reload(characterizer)
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=4,
c = sram_config(word_size=2,
num_words=256,
num_banks=1)
c.words_per_row=4

2
compiler/tests/22_psram_1bank_nomux_func_test.py
View File

@ -38,7 +38,7 @@ class psram_1bank_nomux_func_test(openram_test):
reload(characterizer)
from characterizer import functional, delay
from sram_config import sram_config
c = sram_config(word_size=4,
c = sram_config(word_size=2,
num_words=32,
num_banks=1)
c.words_per_row=1