mirror of https://github.com/VLSIDA/OpenRAM.git
Remove cells from DRC/LVS in the blackbox tech list.
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parent
acbbbe9403
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3eb0dad06a
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@ -42,11 +42,13 @@ def setup_files():
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files = os.listdir(gds_dir)
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nametest = re.compile("\.gds$", re.IGNORECASE)
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gds_files = list(filter(nametest.search, files))
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import tech
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if tech.blackbox_bitcell:
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# Ignore DRC of all bitcells
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nametest = re.compile("cell", re.IGNORECASE)
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gds_files = list(filter(lambda v: not nametest.search(v), gds_files))
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try:
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from tech import blackbox_cells
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gds_files = list(set(gds_files) - set(blackbox_cells))
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except ImportError:
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pass
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return (gds_dir, gds_files)
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@ -62,8 +62,13 @@ def setup_files():
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tempnames[i] = re.sub('\.gds$', '', tempnames[i])
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tempnames[i] = re.sub('\.sp$', '', tempnames[i])
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# remove duplicate base names
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nameset = set(tempnames)
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try:
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from tech import blackbox_cells
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nameset = list(set(tempnames) - set(blackbox_cells))
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except ImportError:
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# remove duplicate base names
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nameset = set(tempnames)
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allnames = list(nameset)
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return (gds_dir, sp_dir, allnames)
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