mirror of https://github.com/VLSIDA/OpenRAM.git
Added method to route between the output of wmask AND array and en of write driver.
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jsowash
parent
aaa1e3a614
commit
d02ea06ff2
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@ -438,7 +438,6 @@ class port_data(design.design):
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wmask_in_name = "wmask_in_{}".format(bit)
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bank_wmask_name = "bank_wmask_{}".format(bit)
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self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name)
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# self.copy_layout_pin(self.write_mask_and_array_inst,"wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit))
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def route_write_mask_and_array_to_write_driver(self,port):
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@ -448,14 +447,7 @@ class port_data(design.design):
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inst1 = self.write_mask_and_array_inst
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inst2 = self.write_driver_array_inst
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# get length of a single driver enable
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driver = factory.create(module_type="write_driver")
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bitcell = factory.create(module_type="bitcell")
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if bitcell.width > driver.width:
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driver_spacing = bitcell.width
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else:
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driver_spacing = driver.width
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i = 0
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for bit in range(self.num_wmasks):
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# Bring write mask AND array output pin to port data level
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self.copy_layout_pin(inst1, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit))
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@ -463,68 +455,34 @@ class port_data(design.design):
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wmask_out_pin = inst1.get_pin("wmask_out_{0}".format(bit))
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wdriver_en_pin = inst2.get_pin("en_{0}".format(bit))
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bitline_pin = inst2.get_pin("data_{}".format(bit))
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half_width = bitline_pin.width() / 2
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width = driver.width
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# The metal2 wdriver_sel_{} wire must hit the en_{} pin after the closest bitline pin that's right of the
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# the wdriver_sel_{} pin in the write driver AND array.
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spacing = 2*drc("metal2_to_metal2")
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middle_of_driver = driver.width/2
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len_no_drc = middle_of_driver + spacing + half_width
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if bit == 0:
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while (wmask_out_pin.lx() > inst2.get_pin("data_{0}".format(i)).rx()):
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i += 1
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length = inst2.get_pin("data_{0}".format(i)).rx() + spacing
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if self.words_per_row == 1:
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length = 3*width + len_no_drc + (bit*driver.width*self.write_size)
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else:
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length = 3*width + self.words_per_row*driver_spacing + len_no_drc + (bit*self.words_per_row*driver_spacing*driver.width*self.write_size)
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# while (wdriver_en_pin.lx() > length):
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# length += driver.width
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i = i + ( bit*self.write_size )
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length = inst2.get_pin("data_{0}".format(i)).rx() + spacing
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offset = vector(length, wdriver_en_pin.cy())
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end_en_pin = vector(length,wmask_out_pin.cy())
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beg_pos = wmask_out_pin.center()
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middle_pos = vector(length,wmask_out_pin.cy())
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end_pos = vector(length, wdriver_en_pin.cy())
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# Add via for the write driver array's enable input
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=offset)
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offset=end_pos)
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self.add_layout_pin_rect_center(text="wdriver_sel_{0}".format(bit),
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layer="metal2",
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offset=offset)
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offset=end_pos)
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# Route between write mask AND array and write driver array
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self.add_path("metal1",[ wmask_out_pin.center(), end_en_pin])
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self.add_path("metal1",[beg_pos, middle_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end_en_pin)
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self.add_path("metal2", [end_en_pin, offset])
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# # get length of a single driver enable
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# self.driver = factory.create(module_type="write_driver")
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# driver_en = self.driver.get_pin("en")
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# len = 2*driver_en.width() + bit*driver_en.width()
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#
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#
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# print(len)
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# while (wdriver_en_pin.lx() > len):
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# len += 2*driver_en.width()
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# print("here")
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# len += 2*driver_en.width()
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# end_en_pin = vector(len,wmask_out_pin.by())
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#
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# offset = vector(len, wdriver_en_pin.cy())
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# spacing = drc("metal2_to_metal2")
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# center_x = wmask_out_pin.cy()
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# center_y = wdriver_en_pin.cx()
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# end_en_pin = vector(wdriver_en_pin.rx(),wmask_out_pin.by())
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#
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# center_wmask = vector(center_x, center_y)
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#
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# self.add_path("metal2", [wmask_out_pin.center(), wdriver_en_pin.rc()])
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#
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# self.add_path("metal2", [wmask_out_pin.center(), wdriver_en_pin.center()])
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# #
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offset=middle_pos)
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self.add_path("metal2", [middle_pos, end_pos])
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def route_column_mux_to_precharge_array(self, port):
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@ -1,4 +1,4 @@
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#!/usr/bin/env python3
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1#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California
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@ -70,7 +70,7 @@ class port_data_test(openram_test):
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self.local_check(a)
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a = factory.create("port_data", sram_config=c, port=1)
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self.local_check(a)
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#
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c.num_words = 32
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c.words_per_row = 2
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factory.reset()
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@ -91,7 +91,7 @@ class port_data_test(openram_test):
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a = factory.create("port_data", sram_config=c, port=1)
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self.local_check(a)
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c.word_size = 2
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c.word_size = 8
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c.num_words = 128
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c.words_per_row = 8
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factory.reset()
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