mirror of https://github.com/VLSIDA/OpenRAM.git
Default tools are calibre except for SCMOS
This commit is contained in:
parent
102758881a
commit
f4599b7121
|
|
@ -18,13 +18,13 @@ temperatures = [25]
|
|||
route_supplies = True
|
||||
check_lvsdrc = True
|
||||
|
||||
if tech_name == "freepdk45":
|
||||
if tech_name.startswith("scn"):
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
else:
|
||||
supply_voltages = [1.0]
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
|
|
|||
|
|
@ -19,13 +19,13 @@ check_lvsdrc = True
|
|||
inline_lvsdrc = True
|
||||
analytical_delay = False
|
||||
|
||||
if tech_name == "freepdk45":
|
||||
if tech_name.startswith("scn"):
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
else:
|
||||
supply_voltages = [1.0]
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
|
|
|||
|
|
@ -14,14 +14,14 @@ process_corners = ["TT"]
|
|||
supply_voltages = [5.0]
|
||||
temperatures = [25]
|
||||
|
||||
if tech_name == "freepdk45":
|
||||
if tech_name.startswith("scn"):
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
else:
|
||||
supply_voltages = [1.0]
|
||||
drc_name = "calibre"
|
||||
lvs_name = "calibre"
|
||||
pex_name = "calibre"
|
||||
else:
|
||||
drc_name = "magic"
|
||||
lvs_name = "netgen"
|
||||
pex_name = "magic"
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue