Move DRC/LVS/PEX tools to tech file.

compiler/globals.py

@@ -448,14 +448,24 @@ def init_paths():
         
 def set_default_corner():
     """ Set the default corner. """
-    
+
+    import tech
     # Set some default options now based on the technology...
     if (OPTS.process_corners == ""):
-        OPTS.process_corners = tech.spice["fet_models"].keys()
+        if OPTS.nominal_corner_only:
+            OPTS.process_corners = ["TT"]
+        else:
+            OPTS.process_corners = tech.spice["fet_models"].keys()
     if (OPTS.supply_voltages == ""):
-        OPTS.supply_voltages = tech.spice["supply_voltages"]
+        if OPTS.nominal_corner_only:
+            OPTS.supply_voltages = [tech.spice["supply_voltages"][1]]
+        else:
+            OPTS.supply_voltages = tech.spice["supply_voltages"]
     if (OPTS.temperatures == ""):
-        OPTS.temperatures = tech.spice["temperatures"]
+        if OPTS.nominal_corner_only:
+            OPTS.temperatures = [tech.spice["temperatures"][1]]
+        else:
+            OPTS.temperatures = tech.spice["temperatures"]
     
     
 def import_tech():

compiler/options.py

@@ -34,6 +34,7 @@ class options(optparse.Values):
     write_size = None
     
     # These will get initialized by the user or the tech file
+    nominal_corner_only = True
     supply_voltages = ""
     temperatures = ""
     process_corners = ""
@@ -85,6 +86,8 @@ class options(optparse.Values):
     check_lvsdrc = False
     # This determines whether LVS and DRC is checked for every submodule.
     inline_lvsdrc = False
+    # Treat the bitcell as a black box (no DRC, LVS, or extraction)
+    blackbox_bitcell = False
     # Remove noncritical memory cells for characterization speed-up
     trim_netlist = False
     # Run with extracted parasitics
@@ -110,8 +113,7 @@ class options(optparse.Values):
     
     # Should we print out the banner at startup
     print_banner = True
-    # Use detailed LEF blockages
-    detailed_blockages = True
+
     # Define the output file paths
     output_path = "."
     # Define the output file base name

compiler/tests/configs/config.py

@@ -11,20 +11,6 @@ num_words = 16
 
 tech_name = OPTS.tech_name
 
-process_corners = ["TT"]
-supply_voltages = [5.0]
-temperatures = [25]
-
 route_supplies = True
 check_lvsdrc = True
 
-if tech_name.startswith("scn"):
-    drc_name = "magic"
-    lvs_name = "netgen"
-    pex_name = "magic"
-else:
-    supply_voltages = [1.0]
-    drc_name = "calibre"
-    lvs_name = "calibre"
-    pex_name = "calibre"
-

compiler/tests/configs/config_back_end.py

@@ -10,22 +10,10 @@ word_size = 1
 num_words = 16
 
 tech_name = OPTS.tech_name
-process_corners = ["TT"]
-supply_voltages = [5.0]
-temperatures = [25]
 
 route_supplies = True
 check_lvsdrc = True
 inline_lvsdrc = True
 analytical_delay = False
 
-if tech_name.startswith("scn"):
-    drc_name = "magic"
-    lvs_name = "netgen"
-    pex_name = "magic"
-else:
-    supply_voltages = [1.0]
-    drc_name = "calibre"
-    lvs_name = "calibre"
-    pex_name = "calibre"
 

compiler/tests/configs/config_front_end.py

@@ -10,18 +10,5 @@ word_size = 1
 num_words = 16
 
 tech_name = OPTS.tech_name
-process_corners = ["TT"]
-supply_voltages = [5.0]
-temperatures = [25]
-
-if tech_name.startswith("scn"):
-    drc_name = "magic"
-    lvs_name = "netgen"
-    pex_name = "magic"
-else:
-    supply_voltages = [1.0]
-    drc_name = "calibre"
-    lvs_name = "calibre"
-    pex_name = "calibre"
 
 

compiler/verify/__init__.py

@@ -17,7 +17,12 @@ If not, OpenRAM will continue as if nothing happened!
 
 import os
 import debug
-from globals import OPTS,find_exe,get_tool
+from globals import OPTS
+from globals import find_exe
+from globals import get_tool
+from tech import drc_name
+from tech import lvs_name
+from tech import pex_name
 import sys
 
 debug.info(1,"Initializing verify...")
@@ -29,29 +34,29 @@ if not OPTS.check_lvsdrc:
     OPTS.pex_exe = None
 else:
     debug.info(1, "Finding DRC/LVS/PEX tools.")    
-    OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], OPTS.drc_name)
-    OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], OPTS.lvs_name)
-    OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], OPTS.pex_name)
+    OPTS.drc_exe = get_tool("DRC", ["calibre","assura","magic"], drc_name)
+    OPTS.lvs_exe = get_tool("LVS", ["calibre","assura","netgen"], lvs_name)
+    OPTS.pex_exe = get_tool("PEX", ["calibre","magic"], pex_name)
 
 if OPTS.drc_exe == None:
-    from .none import run_drc,print_drc_stats
+    from .none import run_drc, print_drc_stats
 elif "calibre"==OPTS.drc_exe[0]:
-    from .calibre import run_drc,print_drc_stats
+    from .calibre import run_drc, print_drc_stats
 elif "assura"==OPTS.drc_exe[0]:
-    from .assura import run_drc,print_drc_stats
+    from .assura import run_drc, print_drc_stats
 elif "magic"==OPTS.drc_exe[0]:
-    from .magic import run_drc,print_drc_stats
+    from .magic import run_drc, print_drc_stats
 else:
     debug.warning("Did not find a supported DRC tool.")
 
 if OPTS.lvs_exe == None:
-    from .none import run_lvs,print_lvs_stats
+    from .none import run_lvs, print_lvs_stats
 elif "calibre"==OPTS.lvs_exe[0]:
-    from .calibre import run_lvs,print_lvs_stats
+    from .calibre import run_lvs, print_lvs_stats
 elif "assura"==OPTS.lvs_exe[0]:
-    from .assura import run_lvs,print_lvs_stats
+    from .assura import run_lvs, print_lvs_stats
 elif "netgen"==OPTS.lvs_exe[0]:
-    from .magic import run_lvs,print_lvs_stats
+    from .magic import run_lvs, print_lvs_stats
 else:
     debug.warning("Did not find a supported LVS tool.")
 

technology/freepdk45/config.py

@@ -0,0 +1,7 @@
+process_corners = ["TT"]
+supply_voltages = [1.0]
+temperatures = [25]
+
+drc_name = "calibre"
+lvs_name = "calibre"
+pex_name = "calibre"

technology/freepdk45/tech/tech.py

@@ -336,3 +336,14 @@ parameter["bitcell_drain_cap"] = 0.1        #In Femto-Farad, approximation of dr
 ##END Spice Simulation Parameters
 ###################################################
 
+###################################################
+##BEGIN Technology Tool Preferences
+###################################################
+
+drc_name = "calibre"
+lvs_name = "calibre"
+pex_name = "calibre"
+
+###################################################
+##END Technology Tool Preferences
+###################################################

technology/scn3me_subm/__init__.py

@@ -35,9 +35,5 @@ except:
     DRCLVS_HOME=OPENRAM_TECH+"/scn3me_subm/tech"
 os.environ["DRCLVS_HOME"] = DRCLVS_HOME
 
-# try:
-#     SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
-# except:
-OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
-os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
+os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
 

technology/scn3me_subm/tech/tech.py

@@ -277,3 +277,15 @@ parameter["bitcell_drain_cap"] = 0.2        #In Femto-Farad, approximation of dr
 ###################################################
 ##END Spice Simulation Parameters
 ###################################################
+
+###################################################
+##BEGIN Technology Tool Preferences
+###################################################
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
+
+###################################################
+##END Technology Tool Preferences
+###################################################

technology/scn4m_subm/__init__.py

@@ -35,9 +35,5 @@ except:
     DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech"
 os.environ["DRCLVS_HOME"] = DRCLVS_HOME
 
-# try:
-#     SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
-# except:
-OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
-os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
+os.environ["SPICE_MODEL_DIR"] = "{0}/models".format(os.path.dirname(__file__))
 

technology/scn4m_subm/config.py

@@ -0,0 +1,7 @@
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"

technology/scn4m_subm/tech/tech.py

@@ -301,3 +301,15 @@ parameter["bitcell_drain_cap"] = 0.2        #In Femto-Farad, approximation of dr
 ###################################################
 ##END Spice Simulation Parameters
 ###################################################
+
+###################################################
+##BEGIN Technology Tool Preferences
+###################################################
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"
+
+###################################################
+##END Technology Tool Preferences
+###################################################