Merge branch 'dev' into tech_migration

compiler/base/hierarchy_spice.py

@@ -226,7 +226,7 @@ class spice():
             subckt_line = list(filter(subckt.search, self.lvs))[0]
             # parses line into ports and remove subckt
             lvs_pins = subckt_line.split(" ")[2:]
-            debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.", -1)
+            debug.check(lvs_pins == self.pins, "LVS and spice file pin mismatch.")
             
     def check_net_in_spice(self, net_name):
         """Checks if a net name exists in the current. Intended to be check nets in hand-made cells."""
@@ -319,7 +319,7 @@ class spice():
             # Including the file path makes the unit test fail for other users.
             # if os.path.isfile(self.sp_file):
             #    sp.write("\n* {0}\n".format(self.sp_file))
-            if lvs_netlist:
+            if lvs_netlist and hasattr(self, "lvs"):
                 sp.write("\n".join(self.lvs))
             else:
                 sp.write("\n".join(self.spice))

compiler/characterizer/lib.py

@@ -45,7 +45,7 @@ class lib:
         """ Determine the load/slews if they aren't specified in the config file. """
         # These are the parameters to determine the table sizes
         #self.load_scales = np.array([0.1, 0.25, 0.5, 1, 2, 4, 8])
-        self.load_scales = np.array([0.25, 1, 8])
+        self.load_scales = np.array([0.25, 1, 4])
         #self.load_scales = np.array([0.25, 1])
         self.load = tech.spice["dff_in_cap"]
         self.loads = self.load_scales*self.load

compiler/modules/dff_buf.py

@@ -91,8 +91,8 @@ class dff_buf(design.design):
     def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",
                                     mod=self.dff)
-        self.connect_inst(props.dff_buff.buf_ports)                                    
-        #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
+
+        self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
 
         self.inv1_inst=self.add_inst(name="dff_buf_inv1",
                                      mod=self.inv1)

compiler/sram/sram.py

@@ -51,6 +51,9 @@ class sram():
     def sp_write(self, name):
         self.s.sp_write(name)
 
+    def lvs_write(self, name):
+        self.s.lvs_write(name)
+        
     def lef_write(self, name):
         self.s.lef_write(name)
 

compiler/sram/sram_base.py

@@ -561,7 +561,7 @@ class sram_base(design, verilog, lef):
             self.add_via_center(layers=self.m2_stack,
                                 offset=out_pos)
             
-    def sp_write(self, sp_name):
+    def sp_write(self, sp_name, lvs_netlist=False):
         # Write the entire spice of the object to the file
         ############################################################
         # Spice circuit
@@ -581,10 +581,13 @@ class sram_base(design, verilog, lef):
         # sp.write(".global {0} {1}\n".format(spice["vdd_name"],
         #                                     spice["gnd_name"]))
         usedMODS = list()
-        self.sp_write_file(sp, usedMODS)
+        self.sp_write_file(sp, usedMODS, lvs_netlist=lvs_netlist)
         del usedMODS
         sp.close()
- 
+
+    def lvs_write(self, sp_name):
+        self.sp_write(sp_name, lvs_netlist=True)
+        
     def get_wordline_stage_efforts(self, inp_is_rise=True):
         """Get the all the stage efforts for each stage in the path from clk_buf to a wordline"""
         stage_effort_list = []

compiler/tests/testutils.py

@@ -39,7 +39,7 @@ class openram_test(unittest.TestCase):
         tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name)
         tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name)
 
-        a.sp_write(tempspice)
+        a.lvs_write(tempspice)
         # cannot write gds in netlist_only mode
         if not OPTS.netlist_only:
             a.gds_write(tempgds)