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2482 Commits

Author SHA1 Message Date
Hunter Nichols 0464e2df5d Allowed bitline checks for multiple ports. 2020-06-30 01:37:52 -07:00
Hunter Nichols c289637dab Allowed sen's from multiple ports to be characterized 2020-06-29 23:18:31 -07:00
mrg 372a8a728e Off by one error in channel spacing 2020-06-29 16:47:34 -07:00
mrg 459e3789b8 Change control layers in sky130. 2020-06-29 16:23:25 -07:00
mrg bec948dcc3 Fix error in when to add vias for array power 2020-06-29 15:28:55 -07:00
mrg 4e7e0c5954 Skip test in sky130 2020-06-29 15:28:16 -07:00
Matt Guthaus e97644c424 Only do reverse lookup on valid interconnect layers since layer numbers can be shared. 2020-06-29 14:42:24 -07:00
mrg 07d0f3af8e Only copy end-cap pins to the bank level 2020-06-29 11:46:59 -07:00
mrg 1bc0775810 Only add pins to periphery 2020-06-29 10:03:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 47f541df0e Fix bugs in channel route. 2020-06-28 16:58:28 -07:00
mrg 5285468380 All bitcells need a vdd/gnd pin 2020-06-28 15:09:47 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 051c8d8697 Only add bitcells to dummy and replica rows and columns (the perimeter) 2020-06-28 14:47:54 -07:00
mrg 709535f90f Fix right perimeter pin coordinate bug 2020-06-28 14:47:17 -07:00
mrg 225fc69420 Use preferred routing direction 2020-06-28 14:29:12 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg bc3de9db05 Pick correct side of pin in channel route. 2020-06-28 14:28:18 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg c10a6a29c0 Simplify precharge pin layer 2020-06-27 08:22:16 -07:00
mrg 609aa98c8b Move write mask pin to left of cell to avoid sense amp 2020-06-27 08:21:53 -07:00
mrg 2bd498c39c Change precharge layer to m3 2020-06-27 08:21:30 -07:00
mrg c07e20cbe4 Move mux select from li to m2 in sky130 2020-06-26 14:27:16 -07:00
mrg 94d7000717 Reduce output clutter from gds write 2020-06-26 12:16:54 -07:00
mrg f57eeb88eb PEP8 cleanup, multiple vdd/gnd support 2020-06-26 11:47:55 -07:00
mrg e23d41c1d4 PEP8 cleanup 2020-06-26 11:47:35 -07:00
mrg 567675ab31 PEP8 cleanup 2020-06-26 11:47:12 -07:00
mrg af4ed3dd6e Skip riscv func test for time sake 2020-06-26 06:50:45 -07:00
mrg d53abba479 Always route the channel route since it is it's own design. 2020-06-25 17:43:44 -07:00
mrg 76e5389c33 Change riscv func test name 2020-06-25 17:43:17 -07:00
mrg 9eb1b500ea Skip phys riscv test 2020-06-25 17:31:23 -07:00
mrg f11afaa63d Refactor channel route to be a design. 2020-06-25 17:30:03 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 66df659ad4 Col decoders are anything not bitcell pitch. 2020-06-25 14:25:48 -07:00
mrg f84ee04fa9 Single bank passing. 
Parameterized gate column mux of dff height.
End-cap only supply option instead of no vdd in bitcell.
 2020-06-25 14:03:59 -07:00
mrg ee0a003298 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-25 08:57:37 -07:00
jcirimel 5941e01b51 add missing parens 2020-06-25 08:02:08 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
jcirimel 812cf11e95 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-06-25 06:32:29 -07:00
jcirimel 57b6d49edb fix pinv size bining 2020-06-25 06:32:07 -07:00
mrg da900b89ba Only expand implants in sky130 2020-06-24 13:48:30 -07:00
mrg ba92467fec Add no well enclosure for techs without wells 2020-06-24 12:07:47 -07:00
mrg 6c523a7556 use add_enclosure for npc contacts 2020-06-24 11:55:44 -07:00
mrg e694622f28 use add_enclosure to extend implants 2020-06-24 11:54:59 -07:00
mrg 4bc3df8931 Add get_tx_insts and expand add_enclosure 2020-06-24 11:54:36 -07:00
mrg 93d65e84e1 Fix power pin layer problems in delay line 2020-06-24 10:26:49 -07:00
mrg 98ec9442c6 Add npc enclosure for pnand2, pnand3, pnor2 2020-06-24 10:00:00 -07:00
mrg 1340908330 Remove fudge factor for pin spacing 2020-06-24 09:24:26 -07:00
mrg cddb16dabc Separate active and poly contact to gate rule 2020-06-24 09:17:39 -07:00
mrg a32b5b13e8 Rename nwell yoffset for consistency 2020-06-24 08:26:15 -07:00
mrg b3d1161957 Add u+x permissions to new tests 2020-06-24 08:19:25 -07:00
Joey Kunzler 22ed725a35 made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test 2020-06-23 18:16:14 -07:00
Joey Kunzler 4e83e8c648 added contact to locali for wmask 2020-06-23 18:13:17 -07:00
mrg 22c821f5d8 Change port_address test to 256 for riscv 2020-06-23 15:40:00 -07:00
mrg cfa234a4d0 Extra space between decoders for well spacing 2020-06-23 15:39:42 -07:00
mrg 83001e1ab5 PEP8 formatting 2020-06-23 15:39:26 -07:00
mrg e849a9b973 Use different LVS libs based on tech and sky130 2020-06-23 14:53:24 -07:00
mrg 031862c749 Add metal enclosure to base case of center via stack. 2020-06-23 11:56:50 -07:00
mrg 1a528f9739 Skip and4_dec test 2020-06-23 10:08:28 -07:00
mrg 7ea3366ef1 Disable magic filter in sky130 2020-06-22 16:58:01 -07:00
mrg 92fc30005c Use factory in and_dec tests 2020-06-22 16:55:49 -07:00
mrg 40edbfa51f Error out on single port in sky130 2020-06-22 15:41:59 -07:00
mrg cd23b31ab4 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-06-22 12:55:45 -07:00
mrg 0926eab9f5 PEP8 formatting 2020-06-22 12:55:18 -07:00
mrg 54120f8405 Add option for removing subckt/instances of cells for row/col caps 2020-06-22 12:35:37 -07:00
mrg a13d535945 PEP8 cleanup 2020-06-22 11:33:02 -07:00
Joey Kunzler 8166adc512 Merge branch 'dev' into s8_update 2020-06-19 15:35:49 -07:00
Joey Kunzler 208c652653 added error for sky130 with invalid x mirroring (for lvs) 2020-06-19 13:59:33 -07:00
mrg a2d160dbf5 Copy magic config for filter code 2020-06-19 13:40:45 -07:00
mrg 5872f553e1 Rename tests for consistency 2020-06-19 08:53:35 -07:00
mrg 239b3ea007 Make wmask test a 1rw/1r 2020-06-19 08:49:48 -07:00
mrg 617a84d4b8 Fix output name of magic gds filter 2020-06-19 07:15:27 -07:00
mrg 94c480911b ngspice raw save doesn't work with measures 2020-06-19 07:09:15 -07:00
mrg 231f90f492 Fix missing space in ptx spice line 2020-06-19 06:47:46 -07:00
mrg 403ea17039 PEP8 formatting 2020-06-18 14:55:01 -07:00
mrg 69f5621245 Save raw file from ngspice 2020-06-18 14:54:36 -07:00
mrg 7dfc462ef6 Add magic filter before calibre for sky130 2020-06-15 13:58:26 -07:00
mrg abb5ff7bae Separate route conditions for s8 2020-06-15 10:30:27 -07:00
mrg e331d6fae8 Permute bus order to avoid conflict in control_logic 2020-06-15 10:25:53 -07:00
mrg a862cf3cb2 Test more single level col mux configs 2020-06-15 10:17:54 -07:00
mrg 4cb827c3d7 Add redundant implant for s8 2020-06-15 10:08:07 -07:00
mrg 355474ce2c Playing around with pnand2 pin spacing rules 2020-06-15 10:07:00 -07:00
mrg 6e0008403e Update new tech name 2020-06-15 10:06:17 -07:00
mrg 79b3b9a8b0 Switch input/output layers for predecodes 2020-06-15 10:06:04 -07:00
mrg 6c04166876 Update port data wmask tests 2020-06-15 06:05:05 -07:00
mrg 02352c35d7 Fix hard coded layer in wmask 2020-06-14 17:10:32 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 9930b5f3f6 Do not run tapless unit tests 2020-06-14 14:18:25 -07:00
mrg 7dc33285a7 Add contact to gate design rule to max for spacing inputs 2020-06-14 14:18:08 -07:00
mrg 8e8a97cc4b Add correct boundary to SRAM 2020-06-14 14:17:35 -07:00
mrg 443c401561 pnand2 B input spaced from top 2020-06-14 14:17:04 -07:00
mrg 91f20f2cf6 Better centering of pinv_dec 2020-06-14 14:09:45 -07:00
mrg 8f1dc7eeea Include mirror/rotate on translate_all boundary update 2020-06-13 06:50:53 -07:00
mrg 33a32101c9 DRC and LVS fixes for pinv_dec 2020-06-12 15:23:51 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
mrg 54e4d147f6 Rail to ptx spacing based on routing layer not m1 2020-06-11 15:03:50 -07:00
mrg e9780ea599 Add non-preferred directions for channel routes 2020-06-11 15:03:36 -07:00
mrg 8d52794c32 Remove printf in precharge 2020-06-11 11:57:52 -07:00
mrg 7ad2d54a69 Add pin and label purposes 2020-06-11 11:54:51 -07:00
mrg 1a2e0046b1 Add contact to gate spacing for precharge 2020-06-11 11:54:34 -07:00
mrg 089331ced3 Add stdc bounding box too 2020-06-11 11:54:16 -07:00
mrg 098219d56c Add npc enclosure to poly contacts 2020-06-11 11:53:59 -07:00
mrg f973dd6a5c Save LVS model with no u too for Calibre 2020-06-11 11:53:34 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg 196e5998c8 Half poly space per cell at top and bottom. 2020-06-10 16:52:51 -07:00
mrg fdf92d0da1 Rename test 14 2020-06-10 16:41:26 -07:00
mrg 0b4b5e7133 More exact input spacing in pnand3 2020-06-10 16:19:24 -07:00
mrg bfd1abc79f Replica column pins start at 0 height. 2020-06-10 14:58:55 -07:00
mrg 469cd260b9 Change bitcell array name to match 2020-06-10 14:54:20 -07:00
mrg f2c45a230e Add new replica column test. Add more skip tests. 2020-06-10 11:00:00 -07:00
mrg 10be2d08b5 Full path to skip tests file 2020-06-10 10:23:05 -07:00
mrg 5e3332453b Allow power pins to start on any layer besides m1 2020-06-10 10:15:23 -07:00
mrg c119e60e79 Add more s8 skip tests 2020-06-10 10:14:52 -07:00
mrg d4fc88124a Rename dff_buf test 2020-06-09 17:18:19 -07:00
mrg 064fe34edf Fix pinvbuf layers 2020-06-09 17:16:35 -07:00
mrg 14782914b3 Remove vertical pand gates 2020-06-09 16:40:59 -07:00
mrg e6babc301d Incrase space for pnand gates 2020-06-09 16:34:15 -07:00
mrg c6b875146d Use local skip file 2020-06-09 16:33:59 -07:00
mrg fd49d3ed6a Add tech specific skip tests for making new techs. 2020-06-09 16:09:15 -07:00
mrg 580b0601b5 Unskip 20_psram_1bank_4mux_1rw_1r_test 2020-06-09 16:04:39 -07:00
mrg a28e747a02 Fix precharge offset. Move well rules to design class. 2020-06-09 15:28:50 -07:00
mrg 148521c458 Remove stdc layer 2020-06-09 13:48:47 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg 8c6d5b49be Consider diffusion spacing in active offset 2020-06-09 13:09:52 -07:00
mrg 77fb7017c4 Merge branch 'tech_migration' into dev 2020-06-08 12:54:41 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
Aditi Sinha c39c0efd39 Updated spare col tests 2020-06-08 16:38:18 +00:00
Aditi Sinha 300522a1a8 Change spare enable pins offset to lower right 2020-06-08 14:31:46 +00:00
Aditi Sinha ef940e0dc5 Fixes for functional test of spare cols 2020-06-08 05:02:04 +00:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
jcirimel 5d5ed552e3 Merge branch 'dev' into discrete_models 2020-06-06 01:48:06 -07:00
mrg 0837432d45 Wordline route layers and (optional) via. 2020-06-05 16:47:22 -07:00
jcirimel 9857a3f7e7 Merge branch 'dev' into discrete_models 2020-06-05 16:47:01 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg 2e7f9395f2 Rename 05 test to 14 2020-06-05 09:57:16 -07:00
mrg 68ffb94d2e Rename 05 test to 14 2020-06-05 09:55:57 -07:00
mrg fb3acae908 PEP8 format testutils. 2020-06-05 09:44:30 -07:00
jcirimel 08f6bd8d24 optimize tx binning for area 2020-06-05 02:53:03 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg e06dc3810a Move precharge pin to bottom 2020-06-04 12:12:19 -07:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
mrg 7aafa43897 Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
mrg 249b5355ba Adjust rbl route 2020-06-03 17:08:04 -07:00
mrg 77c95b28da Rename precharge test 2020-06-03 16:39:46 -07:00
mrg 3927c62e32 Undo extra space due to nwell spacing 2020-06-03 16:39:33 -07:00
mrg b2b7e7800b Undo same bitline pitch 2020-06-03 16:39:05 -07:00
mrg 4183638f03 Align precharge bitlines with col mux 2020-06-03 16:05:57 -07:00
mrg 4bc1e9a026 Fix the bitline spacing in the column mux to a constant. 2020-06-03 15:47:03 -07:00
mrg 3b1fe26d25 Spacing between decoder and driver for s8 2020-06-03 14:33:30 -07:00
mrg e93f3f1d2e Add 1rw_1r tests 2020-06-03 14:30:15 -07:00
mrg b78166c044 Merge branch 'dev' into tech_migration 2020-06-03 14:08:22 -07:00
Joey Kunzler 7a602b75a4 keep dev routing changes to hierarchy_layout 2020-06-03 12:54:15 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
mrg 38f5e8b865 Add col mux tests for multiport 2020-06-03 10:01:02 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg fdf51c5a00 Add port option to precharge array 2020-06-02 11:44:22 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg 45b0601e4b Fix via directions in s8 col mux 2020-06-02 11:43:31 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg 620604603c Fixed offset jogs 2020-06-02 10:08:37 -07:00
mrg b0aa70ffda Fix precharge vdd route layer 2020-06-02 09:23:27 -07:00
Joey Kunzler b39579c109 temp drc fix for regression tests 2020-06-01 20:55:15 -07:00
mrg 9ecf98a4c3 SRAM factory uses default name for first instance even if it has arguments. 2020-06-01 16:46:22 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
Joey Kunzler b00163e4e1 lvs fix for regression tests 2020-05-29 13:50:34 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
jcirimel 575278998d write only used bitcells to top level in stim and pex output 2020-05-28 23:56:15 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha c14190c5aa Changes in control logic for spare columns 2020-05-14 10:41:54 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
mrg a305d788d7 Vertical gates need both well contacts. 2020-05-13 16:54:35 -07:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
mrg f8bcc54338 Determine width after routing with no well contacts. 2020-05-13 16:04:38 -07:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg 617bf302d1 Add option to remove wells. Save area in pgates with redundant wells. 2020-05-13 14:46:42 -07:00
mrg 848241a3ad PEP8 cleanup 2020-05-11 16:22:17 -07:00
mrg c96a6d0b9d Add no well option. Add stack gates vertical option. 2020-05-11 16:22:08 -07:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Aditi Sinha 5c50cf234b Fixed lvs errors for spare columns 2020-05-09 07:56:19 +00:00
jcirimel 5666e79287 Merge branch 'dev' into discrete_models 2020-05-08 03:13:16 -07:00
Joey Kunzler e642b8521b increase col_mux bitline spacing to fix cyclic vcg 2020-05-06 13:02:33 -07:00
jcirimel d8a51ecafb remove prints, scaling bug fix 2020-05-05 21:59:28 -07:00
jcirimel 71a1dd8f38 fix tx binning in col mux for memories with >1 word per row 2020-05-05 16:35:51 -07:00
Joey Kunzler 91dbbed9ba added horizontal trunk route edit to vertical trunk route 2020-05-05 12:18:26 -07:00