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Change port_address test to 256 for riscv

This commit is contained in:
mrg 2020-06-23 15:40:00 -07:00
parent cfa234a4d0
commit 22c821f5d8
1 changed files with 2 additions and 2 deletions
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4
compiler/tests/18_port_address_1rw_1r_test.py
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@ -30,8 +30,8 @@ class port_address_1rw_1r_test(openram_test):
a = factory.create("port_address", cols=16, rows=16)
self.local_check(a)
debug.info(1, "Port address 512 rows")
a = factory.create("port_address", cols=256, rows=512)
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256)
self.local_check(a)
globals.end_openram()