mirror of https://github.com/VLSIDA/OpenRAM.git
Error out on single port in sky130
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@ -10,7 +10,7 @@ import utils
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from tech import GDS, layer
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from tech import cell_properties as props
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import bitcell_base
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from globals import OPTS
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class bitcell(bitcell_base.bitcell_base):
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"""
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@ -50,6 +50,8 @@ class bitcell(bitcell_base.bitcell_base):
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self.pin_map = bitcell.pin_map
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self.add_pin_types(self.type_list)
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self.nets_match = self.do_nets_exist(self.storage_nets)
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debug.check(OPTS.tech_name != "sky130", "sky130 does not yet support single port cells")
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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