mirror of https://github.com/VLSIDA/OpenRAM.git
Add npc enclosure for pnand2, pnand3, pnor2
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1340908330
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@ -43,6 +43,9 @@ class pgate(design.design):
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self.route_layer_space = getattr(self, "{}_space".format(self.route_layer))
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self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer))
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# hack for enclosing input pin with npc
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self.input_pin_vias = []
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# This is the space from a S/D contact to the supply rail
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contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space
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# This is a poly-to-poly of a flipped cell
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@ -132,6 +135,8 @@ class pgate(design.design):
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offset=contact_offset,
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directions=directions)
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self.input_pin_vias.append(via)
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self.add_layout_pin_rect_center(text=name,
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layer=self.route_layer,
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offset=contact_offset,
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@ -146,6 +151,28 @@ class pgate(design.design):
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height=contact.poly_contact.first_layer_width,
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width=left_gate_offset.x - contact_offset.x)
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def enclose_npc(self):
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""" Enclose the poly contacts with npc layer """
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ll = None
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ur = None
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for via in self.input_pin_vias:
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# Find ll/ur
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if not ll:
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ll = via.ll()
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else:
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ll = ll.min(via.ll())
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if not ur:
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ur = via.ur()
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else:
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ur = ur.max(via.ur())
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npc_enclose_poly = drc("npc_enclose_poly")
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npc_enclose_offset = vector(npc_enclose_poly, npc_enclose_poly)
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self.add_rect(layer="npc",
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offset=ll - npc_enclose_offset,
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width=(ur.x - ll.x) + 2 * npc_enclose_poly,
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height=(ur.y - ll.y) + 2 * npc_enclose_poly)
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def extend_wells(self):
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""" Extend the n/p wells to cover whole cell """
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@ -212,6 +212,10 @@ class pnand2(pgate.pgate):
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"B",
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position="center")
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if OPTS.tech_name == "sky130":
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self.enclose_npc()
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def route_output(self):
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""" Route the Z output """
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@ -246,6 +246,9 @@ class pnand3(pgate.pgate):
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self.inputC_yoffset,
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"C",
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position="right")
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if OPTS.tech_name == "sky130":
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self.enclose_npc()
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def route_output(self):
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""" Route the Z output """
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@ -211,6 +211,9 @@ class pnor2(pgate.pgate):
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self.output_yoffset = self.inputA_yoffset + self.m1_nonpref_pitch
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if OPTS.tech_name == "sky130":
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self.enclose_npc()
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def route_output(self):
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""" Route the Z output """
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# PMOS2 (right) drain
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