fix tx binning in col mux for memories with >1 word per row

compiler/pgates/pgate.py

@@ -286,9 +286,10 @@ class pgate(design.design):
         self.width = max(self.nwell_contact.rx(), self.pwell_contact.rx()) + self.m1_space + 0.5 * contact.m1_via.width
         self.well_width = self.width + 2 * self.nwell_enclose_active
         # Height is an input parameter, so it is not recomputed.
-    
-    def bin_width(self, tx_type, target_width):
 
+    @staticmethod
+    def bin_width(tx_type, target_width):
+        
         if tx_type == "nmos":
             bins = nmos_bins[drc("minwidth_poly")]
         elif tx_type == "pmos":

compiler/pgates/precharge.py

@@ -80,7 +80,7 @@ class precharge(design.design):
         Initializes the upper and lower pmos
         """
         if(OPTS.tech_name == "s8"):
-            (self.ptx_width, self.ptx_mults) = pgate.bin_width(self, "pmos", self.ptx_width)
+            (self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width)
         self.pmos = factory.create(module_type="ptx",
                                    width=self.ptx_width,
                                    mults=self.ptx_mults,

compiler/pgates/ptx.py

@@ -14,7 +14,7 @@ import contact
 import logical_effort
 import os
 from globals import OPTS
-
+from pgate import pgate
 
 class ptx(design.design):
     """
@@ -109,6 +109,7 @@ class ptx(design.design):
         perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
         if OPTS.tech_name == "s8":
             # s8 technology is in microns
+            (self.width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width)
             main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
                                                                       self.mults,
                                                                       self.tx_width,