mirror of https://github.com/VLSIDA/OpenRAM.git
Add correct boundary to SRAM
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@ -124,6 +124,8 @@ class sram_base(design, verilog, lef):
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highest_coord = self.find_highest_coords()
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self.width = highest_coord[0]
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self.height = highest_coord[1]
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self.add_boundary(ll=vector(0, 0),
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ur=vector(self.width, self.height))
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start_time = datetime.datetime.now()
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# We only enable final verification if we have routed the design
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@ -142,7 +144,7 @@ class sram_base(design, verilog, lef):
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for inst in self.insts:
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self.copy_power_pins(inst, "vdd")
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self.copy_power_pins(inst, "gnd")
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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return
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