mirror of https://github.com/VLSIDA/OpenRAM.git
write only used bitcells to top level in stim and pex output
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parent
0f9e38881c
commit
575278998d
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@ -58,14 +58,20 @@ class stimuli():
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for pin in pins:
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self.sf.write("{0} ".format(pin))
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for bank in range(OPTS.num_banks):
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for row in range(int(OPTS.num_words / OPTS.words_per_row)):
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for col in range(int(OPTS.word_size * OPTS.words_per_row)):
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self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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row = int(OPTS.num_words / OPTS.words_per_row) - 1
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col = int(OPTS.word_size * OPTS.words_per_row) - 1
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self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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# can't add all bitcells to top level due to ngspice max port count of 1005
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# for row in range(int(OPTS.num_words / OPTS.words_per_row)):
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# for col in range(int(OPTS.word_size * OPTS.words_per_row)):
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# self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
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# self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
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for bank in range(OPTS.num_banks):
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for col in range(OPTS.word_size * OPTS.words_per_row):
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for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
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self.sf.write("bl{0}_{2} ".format(port, row, col))
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self.sf.write("br{0}_{2} ".format(port, row, col))
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self.sf.write("bl{0}_{1} ".format(port, col))
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self.sf.write("br{0}_{1} ".format(port, col))
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self.sf.write("s_en{0} ".format(bank))
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@ -415,14 +415,15 @@ def correct_port(name, output_file_name, ref_file_name):
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bitcell_list = "+ "
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for bank in range(OPTS.num_banks):
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for row in range(int(OPTS.num_words / OPTS.words_per_row)):
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for col in range(int(OPTS.word_size * OPTS.words_per_row)):
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row, col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row, col)
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for bank in range(OPTS.num_banks):
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row = int(OPTS.num_words / OPTS.words_per_row) - 1
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col = int(OPTS.word_size * OPTS.words_per_row) - 1
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bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col)
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bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col)
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for col in range(OPTS.word_size * OPTS.words_per_row):
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for port in range(OPTS.num_r_ports + OPTS.num_w_ports + OPTS.num_rw_ports):
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bitcell_list += "bl{0}_{2} ".format(bank, row, col)
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bitcell_list += "br{0}_{2} ".format(bank, row, col)
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bitcell_list += "bl{0}_{1} ".format(bank, col)
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bitcell_list += "br{0}_{1} ".format(bank, col)
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bitcell_list += "\n"
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control_list = "+ "
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