mirror of https://github.com/VLSIDA/OpenRAM.git
Incrase space for pnand gates
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@ -177,9 +177,9 @@ class pnand2(pgate.pgate):
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# Top of NMOS drain
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nmos_pin = self.nmos2_inst.get_pin("D")
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bottom_pin_offset = nmos_pin.uy()
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self.inputA_yoffset = bottom_pin_offset + self.m1_pitch
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bottom_pin = self.nmos2_inst.get_pin("D")
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self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch,
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self.nmos2_inst.uy() + self.poly_to_active)
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self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch
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@ -212,10 +212,9 @@ class pnand3(pgate.pgate):
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pmos_drain_bottom = self.pmos1_inst.get_pin("D").by()
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self.output_yoffset = pmos_drain_bottom - 0.5 * self.route_layer_width - self.route_layer_space
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# This is a more compact offset, but the bottom one works better in the decoders to "center" the pins
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# in the height of the gates
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self.inputA_yoffset = self.output_yoffset - 0.5 * self.route_layer_width - self.route_layer_space
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# self.inputA_yoffset = self.output_yoffset - self.m1_pitch
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bottom_pin = self.nmos1_inst.get_pin("D")
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self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch,
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self.nmos1_inst.uy() + self.poly_to_active)
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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@ -223,14 +222,14 @@ class pnand3(pgate.pgate):
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position="left")
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# Put B right on the well line
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self.inputB_yoffset = self.inputA_yoffset - self.m1_pitch
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self.inputB_yoffset = self.inputA_yoffset + self.m1_pitch
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self.route_input_gate(self.pmos2_inst,
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self.nmos2_inst,
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self.inputB_yoffset,
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"B",
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position="center")
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self.inputC_yoffset = self.inputB_yoffset - self.m1_pitch
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self.inputC_yoffset = self.inputB_yoffset + self.m1_pitch
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self.route_input_gate(self.pmos3_inst,
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self.nmos3_inst,
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self.inputC_yoffset,
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