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Rail to ptx spacing based on routing layer not m1

This commit is contained in:
mrg 2020-06-11 15:03:50 -07:00
parent e9780ea599
commit 54e4d147f6
1 changed files with 1 additions and 1 deletions
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2
compiler/pgates/pgate.py
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@ -44,7 +44,7 @@ class pgate(design.design):
self.route_layer_pitch = getattr(self, "{}_pitch".format(self.route_layer))
# This is the space from a S/D contact to the supply rail
contact_to_vdd_rail_space = 0.5 * self.m1_width + self.m1_space
contact_to_vdd_rail_space = 0.5 * self.route_layer_width + self.route_layer_space
# This is a poly-to-poly of a flipped cell
poly_to_poly_gate_space = self.poly_extend_active + 0.5 * self.poly_space