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Change L shape of rbl route

This commit is contained in:
mrg 2020-06-04 11:03:39 -07:00
parent 7aafa43897
commit 717188f85c
1 changed files with 3 additions and 1 deletions
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4
compiler/sram/sram_1bank.py
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@ -320,7 +320,9 @@ class sram_1bank(sram_base):
# Only input (besides pins) is the replica bitline
src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
self.connect_hbus(src_pin, dest_pin)
self.add_wire(self.m2_stack[::-1],
[src_pin.center(), vector(src_pin.cx(), dest_pin.cy()), dest_pin.rc()])
# self.connect_hbus(src_pin, dest_pin)
def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """