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Use factory in and_dec tests

This commit is contained in:
mrg 2020-06-22 16:55:49 -07:00
parent 40edbfa51f
commit 92fc30005c
3 changed files with 22 additions and 13 deletions
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11
compiler/tests/04_and2_dec_test.py
View File

@ -23,10 +23,13 @@ class and2_dec_test(openram_test):
global verify
import verify
import and2_dec
debug.info(2, "Testing and2 gate 4x")
a = and2_dec.and2_dec(name="and2x4", size=4)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and2_dec gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
globals.end_openram()

11
compiler/tests/04_and3_dec_test.py
View File

@ -23,10 +23,13 @@ class and3_dec_test(openram_test):
global verify
import verify
import and3_dec
debug.info(2, "Testing and3 gate 4x")
a = and3_dec.and3_dec(name="and3x4", size=4)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and3_dec gate")
a = factory.create(module_type="and3_dec")
self.local_check(a)
globals.end_openram()

13
compiler/tests/04_and4_dec_test.py
View File

@ -15,7 +15,7 @@ from globals import OPTS
from sram_factory import factory
import debug
class and3_dec_test(openram_test):
class and4_dec_test(openram_test):
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
@ -23,10 +23,13 @@ class and3_dec_test(openram_test):
global verify
import verify
import and3_dec
debug.info(2, "Testing and3 gate 4x")
a = and3_dec.and3_dec(name="and3x4", size=4)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and4_dec gate")
a = factory.create(module_type="and4_dec")
self.local_check(a)
globals.end_openram()