mirror of https://github.com/VLSIDA/OpenRAM.git
Skip phys riscv test
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@ -15,8 +15,8 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 22_sram_1rw_1r_1bank_nomux_func_test")
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class psram_1bank_nomux_func_test(openram_test):
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@unittest.skip("SKIPPING 50_riscv_phys_test")
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class riscv_phys_test(openram_test):
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def runTest(self):
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config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
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