mirror of https://github.com/VLSIDA/OpenRAM.git
Add metal enclosure to base case of center via stack.
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@ -599,6 +599,10 @@ class layout():
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"""
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if from_layer == to_layer:
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# In the case where we have no vias added, make sure that there is at least
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# a metal enclosure. This helps with center-line path routing.
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self.add_rect_center(layer=from_layer,
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offset=offset)
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return last_via
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from_id = layer_indices[from_layer]
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