mirror of https://github.com/VLSIDA/OpenRAM.git
Skip riscv func test for time sake
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@ -15,6 +15,7 @@ from globals import OPTS
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from sram_factory import factory
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import debug
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@unittest.skip("SKIPPING 50_riscv_func_test")
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class riscv_func_test(openram_test):
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def runTest(self):
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