mirror of https://github.com/VLSIDA/OpenRAM.git
Add redundant implant for s8
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parent
355474ce2c
commit
4cb827c3d7
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@ -11,7 +11,7 @@ from tech import drc, layer
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from vector import vector
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from sram_factory import factory
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import logical_effort
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from utils import round_to_grid
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from globals import OPTS
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class single_level_column_mux(pgate.pgate):
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@ -113,18 +113,21 @@ class single_level_column_mux(pgate.pgate):
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + max(self.active_space,self.poly_space))
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+ vector(0, self.nmos.active_height + max(self.active_space, self.poly_space))
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self.nmos_upper = self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos_upper_position)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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if OPTS.tech_name == "sky130":
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self.add_implants()
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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# offset is the top of the lower nmos' diffusion
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# height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space)
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offset = self.nmos_lower.get_pin("G").ul() - vector(0,self.poly_extend_active)
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offset = self.nmos_lower.get_pin("G").ul() - vector(0, self.poly_extend_active)
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height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y
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self.add_rect(layer="poly",
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offset=offset,
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@ -183,13 +186,26 @@ class single_level_column_mux(pgate.pgate):
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vector(nmos_lower_s_pin.cx(), br_out_pin.uy()),
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nmos_lower_s_pin.center()])
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# halfway up, move over
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mid1 = br_pin.bc().scale(1,0.5) \
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+ nmos_lower_d_pin.uc().scale(0,0.5)
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mid2 = br_pin.bc().scale(0,0.5) \
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+ nmos_lower_d_pin.uc().scale(1,0.5)
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mid1 = br_pin.bc().scale(1, 0.5) \
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+ nmos_lower_d_pin.uc().scale(0, 0.5)
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mid2 = br_pin.bc().scale(0, 0.5) \
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+ nmos_lower_d_pin.uc().scale(1, 0.5)
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self.add_path(self.col_mux_stack[2],
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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def add_implants(self):
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"""
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Add top-to-bottom implants for adjacency issues in s8.
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"""
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# Route to the bottom
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ll = (self.nmos_lower.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0)
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# Don't route to the top
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ur = self.nmos_upper.ur() + vector(self.implant_enclose_active, 0)
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self.add_rect("nimplant",
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ll,
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ur.x - ll.x,
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ur.y - ll.y)
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def add_pn_wells(self):
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"""
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Add a well and implant over the whole cell. Also, add the
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@ -209,8 +225,8 @@ class single_level_column_mux(pgate.pgate):
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offset=active_pos)
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# Add the M1->..->power_grid_layer stack
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self.add_power_pin(name = "gnd",
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loc = active_pos,
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self.add_power_pin(name="gnd",
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loc=active_pos,
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start_layer="m1")
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# Add well enclosure over all the tx and contact
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