mirror of https://github.com/VLSIDA/OpenRAM.git
Add option for removing subckt/instances of cells for row/col caps
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parent
a13d535945
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54120f8405
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@ -40,6 +40,8 @@ class spice():
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# THE CONNECTIONS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the
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# Spice format)
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self.conns = []
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# If this is set, it will out output subckt or isntances of this (for row/col caps etc.)
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self.no_instances = False
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# Keep track of any comments to add the the spice
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try:
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self.commments
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@ -264,7 +266,9 @@ class spice():
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Writes the spice subcircuit from the library or the dynamically generated one
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"""
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if not self.spice:
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if self.no_instances:
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return
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elif not self.spice:
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# If spice isn't defined, we dynamically generate one.
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# recursively write the modules
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@ -303,6 +307,9 @@ class spice():
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# these are wires and paths
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if self.conns[i] == []:
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continue
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# Instance with no devices in it needs no subckt/instance
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if self.insts[i].mod.no_instances:
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continue
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if lvs_netlist and hasattr(self.insts[i].mod, "lvs_device"):
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sp.write(self.insts[i].mod.lvs_device.format(self.insts[i].name,
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" ".join(self.conns[i])))
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@ -41,3 +41,4 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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self.height = col_cap_bitcell_1rw_1r.height
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self.pin_map = col_cap_bitcell_1rw_1r.pin_map
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self.add_pin_types(self.type_list)
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self.no_instances = True
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@ -41,3 +41,4 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
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self.height = row_cap_bitcell_1rw_1r.height
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self.pin_map = row_cap_bitcell_1rw_1r.pin_map
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self.add_pin_types(self.type_list)
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self.no_instances = True
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