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OpenRAM
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2482 Commits

Author SHA1 Message Date
mrg 17504a7da3 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-18 09:01:41 -07:00
mrg bc974ff78e Update replica column unit tests for new refactor 2020-08-18 08:56:24 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 99e252d6d4 Update interface of RBL array 2020-08-17 17:19:07 -07:00
mrg b1e55f9072 Add local bitcell array 2020-08-17 15:14:42 -07:00
mrg 3a692e2846 Comment updates 2020-08-17 14:35:39 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 94bfad4113 Horizontal gnd vias for unused array inputs 2020-08-17 13:24:34 -07:00
mrg bddb251a84 More room for power contacts 2020-08-17 12:32:44 -07:00
mrg 2c43d315db Revert gds readonly true 2020-08-17 12:19:23 -07:00
mrg 35a1b00aa0 Extra space for unused wl contacts 2020-08-14 14:23:40 -07:00
mrg 170e3feb7d Fix order of replica wordlines and bitlines 2020-08-14 14:14:49 -07:00
mrg 604e433e22 Add readonly true for Magic scripts 2020-08-14 10:40:31 -07:00
mrg 2ac04efe2e Must connect for replica cells other than top/bottom 2020-08-13 16:26:19 -07:00
mrg 797c41c750 Skip local bitcell array test 2020-08-13 14:36:39 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg 8dbaa66aa5 Merge branch 'super' into dev 2020-08-12 14:25:13 -07:00
mrg 7ac4574e4f Use micron units for all simulation in sky130 2020-08-12 13:54:55 -07:00
mrg 5fc6438553 Fix pinv_dec super call 2020-08-12 13:22:28 -07:00
mrg 15c8c200f3 Undo super() in measurement abstract class 2020-08-12 12:10:12 -07:00
mrg 55814a8f74 Fix syntax errors in pgates for super edits 2020-08-12 11:15:32 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
mrg a55909930f Replace replcia_bitcell_array with new one in bank 2020-08-12 09:49:14 -07:00
mrg 8e890c2014 Replica bitcell with all the fixings 2020-08-11 15:00:29 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg eef97ff215 Reabstracting bit and word line names. 2020-08-06 11:17:49 -07:00
mrg 037de96989 Merge branch 'dev' into wlbuffer 2020-08-05 10:37:29 -07:00
mrg 528cb07635 Merge branch 'dev' into wlbuffer 2020-08-05 10:01:43 -07:00
jcirimel 38648027d0 fix pinv unit test 2020-08-04 04:40:20 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
Bob Vanhoof 487bb6c6e9 Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate 2020-08-03 09:32:27 +02:00
jcirimel 3221b4ec57 update to new metal stack names 2020-07-31 05:27:19 -07:00
Bob Vanhoof dc55ededc1 fix regession tests after calibre fix 2020-07-31 12:51:34 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
mrg 8fa0065aaf Undo PR 82 changes -- broke unit test. 2020-07-30 11:09:19 -07:00
mrg a663d903c5 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-30 08:44:25 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
Hunter Nichols c6f2edc20d Changed warning message for multiport analytical characterization. 2020-07-29 19:50:06 -07:00
mrg 64d61f4d56 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 12:16:41 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
mrg 8a2fa90cd5 Merge remote-tracking branch 'private/dev' into dev 2020-07-29 10:11:26 -07:00
mrg 2fa561f98f Local bitcell array edits. Skip test by default. 2020-07-29 10:08:13 -07:00
Hunter Nichols b4dafac489 Fixed issue with sen measurement not being added 2020-07-27 23:55:03 -07:00
mrg c260297366 Allow replica_bitcell_array without the replica columns for local wordlines. 2020-07-27 16:22:21 -07:00
Hunter Nichols 9ea3616260 Changed multiport characterization warning to better fit 2020-07-27 15:47:02 -07:00
Hunter Nichols c65178f86c Fixed issue with sen delay measure getting mixed with voltage checks 2020-07-27 15:43:50 -07:00
mrg 69cab42676 Add pbuf_dec gate 2020-07-27 13:59:55 -07:00
mrg 26b01e37c6 Fix pbuf test info 2020-07-27 13:59:35 -07:00
mrg 2991534d3f Drafting local bitline stuff. 2020-07-23 17:15:39 -07:00
mrg e1967dc548 Draft local and global arrays. Ensure rows before cols in usage. 2020-07-23 14:43:14 -07:00
mrg 317662d4aa Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-23 14:17:52 -07:00
mrg b7c43ae674 Fix 1w/1r example 2020-07-23 14:17:13 -07:00
jcirimel 1d9296ceb1 fix magic.py conflict 2020-07-21 11:50:25 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg 2ccf3aea3b Set channel route height and width (of routes, not pins) 2020-07-20 13:25:47 -07:00
mrg f87b427f76 Add parent to channel route for dumpign debug gds. 2020-07-20 12:03:25 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg 7385decbff Add channel route cyclic VCG debugging. 2020-07-20 12:02:30 -07:00
mrg 9d5d632d1a Pins may be below the channel. 2020-07-16 14:23:48 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg 919e6a5027 Merge remote-tracking branch 'private/dev' into dev 2020-07-15 19:47:44 -07:00
mrg c7bc01c3a9 Clean up binning. Fix mults to 1 for certain gates. 2020-07-15 17:15:42 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg ed9d32c7bc OpenRAM 1.1.6 2020-07-13 16:26:25 -07:00
mrg e502ee02be Place before computing height of col mux. 2020-07-13 15:51:46 -07:00
mrg 2b7d89d2c1 Fix netlist_only in sky130 2020-07-13 14:59:31 -07:00
mrg e49236f8fc Default drc and lvs errors is skipped. 2020-07-13 14:08:00 -07:00
mrg 716798baae Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors. 2020-07-13 13:01:00 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
mrg 27166c75f0 Don't remove temp files during regular openram runs. 2020-07-03 07:00:56 -07:00
mrg 5dde466ab9 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-07-03 06:55:45 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
Hunter Nichols 206b02a7ee Merge branch 'dev' into characterizer_bug_fixes 2020-07-02 18:00:41 -07:00
Hunter Nichols fb34338fdf Removed debug statements 2020-07-02 18:00:02 -07:00
Hunter Nichols 119bd94689 Fixed warnings with single port characterization. Cleaned up some signal names. 2020-07-02 15:43:23 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg bed2e36550 Simplify write mask supply via logic 2020-07-01 14:44:48 -07:00
mrg 8cd1cba818 Fix missing via in wmask driver 2020-07-01 14:44:18 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg bb18d05f75 Move control output via inside module instead of perimeter 2020-07-01 11:33:25 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg b07f30cb9e Missing output via in control logic 2020-06-30 16:23:07 -07:00
mrg 3379f46da1 Fail unit test, but mention if LVS passes and DRC fails. 2020-06-30 16:22:44 -07:00
mrg 0a87691176 Run Calibre LVS even if DRC fails. 2020-06-30 15:27:10 -07:00
mrg c1fedda575 Modifications for min area metal. 
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
 2020-06-30 15:07:34 -07:00
mrg 011ac2fc05 Don't route to clk to perimeter on m2 2020-06-30 13:57:45 -07:00
mrg a48ea52253 Add missing contact to vdd pins. 2020-06-30 13:26:38 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg eb11ac22f3 Widen pitch of control bus in bank. 2020-06-30 10:58:09 -07:00
mrg 8cedeeb3d9 Widen pitch of control bus in bank. 2020-06-30 10:57:41 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00