mirror of https://github.com/VLSIDA/OpenRAM.git
keep dev routing changes to hierarchy_layout
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6430aad857
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@ -701,7 +701,7 @@ class layout():
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boundary = [self.find_lowest_coords(),
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self.find_highest_coords()]
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debug.check(boundary[0] and boundary[1], "No shapes to make a boundary.")
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height = boundary[1][1] - boundary[0][1]
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width = boundary[1][0] - boundary[0][0]
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(layer_number, layer_purpose) = techlayer[boundary_layer]
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@ -1008,13 +1008,8 @@ class layout():
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max_x = max([pin.center().x for pin in pins])
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min_x = min([pin.center().x for pin in pins])
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# max_x_lc & min_x_rc are for routing to/from the edge of the pins
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# to increase spacing between contacts of different nets
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max_x_lc = max([pin.lc().x for pin in pins])
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min_x_rc = min([pin.rc().x for pin in pins])
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# if we are less than a pitch, just create a non-preferred layer jog
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if max_x_lc - min_x_rc <= pitch:
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if max_x - min_x <= pitch:
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half_layer_width = 0.5 * drc["minwidth_{0}".format(self.vertical_layer)]
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# Add the horizontal trunk on the vertical layer!
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@ -1035,15 +1030,7 @@ class layout():
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# Route each pin to the trunk
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for pin in pins:
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# If there is sufficient space, Route from the edge of the pins
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# Otherwise, route from the center of the pins
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if max_x_lc - min_x_rc > pitch:
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if pin.center().x == max_x:
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mid = vector(pin.lc().x, trunk_offset.y)
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else:
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mid = vector(pin.rc().x, trunk_offset.y)
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else:
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mid = vector(pin.center().x, trunk_offset.y)
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mid = vector(pin.center().x, trunk_offset.y)
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self.add_path(self.vertical_layer, [pin.center(), mid])
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self.add_via_center(layers=layer_stack,
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offset=mid)
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@ -1060,13 +1047,8 @@ class layout():
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max_y = max([pin.center().y for pin in pins])
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min_y = min([pin.center().y for pin in pins])
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# max_y_bc & min_y_uc are for routing to/from the edge of the pins
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# to reduce spacing between contacts of different nets
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max_y_bc = max([pin.bc().y for pin in pins])
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min_y_uc = min([pin.uc().y for pin in pins])
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# if we are less than a pitch, just create a non-preferred layer jog
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if max_y_bc - min_y_uc <= pitch:
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if max_y - min_y <= pitch:
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half_layer_width = 0.5 * drc["minwidth_{0}".format(self.horizontal_layer)]
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@ -1088,17 +1070,6 @@ class layout():
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# Route each pin to the trunk
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for pin in pins:
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# This code block currently causes drc violations for the topmost
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# port when using multiport, TODO: fix or remove this block
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# # If there is sufficient space, Route from the edge of the pins
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# # Otherwise, route from the center of the pins
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# if max_y_bc - min_y_uc > pitch:
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# if pin.center().y == max_y:
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# mid = vector(trunk_offset.x, pin.bc().y)
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# else:
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# mid = vector(trunk_offset.x, pin.uc().y)
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# else:
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# mid = vector(trunk_offset.x, pin.center().y)
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mid = vector(trunk_offset.x, pin.center().y)
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self.add_path(self.horizontal_layer, [pin.center(), mid])
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self.add_via_center(layers=layer_stack,
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