mirror of https://github.com/VLSIDA/OpenRAM.git
pnand2 B input spaced from top
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commit
443c401561
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@ -12,6 +12,7 @@ from globals import OPTS
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from vector import vector
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import logical_effort
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from sram_factory import factory
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import contact
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class pnand2(pgate.pgate):
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@ -177,11 +178,26 @@ class pnand2(pgate.pgate):
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# Top of NMOS drain
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bottom_pin = self.nmos2_inst.get_pin("D")
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self.inputA_yoffset = max(bottom_pin.uy() + self.m1_pitch,
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self.nmos2_inst.uy() + self.poly_to_active)
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self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch
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bottom_pin = self.nmos1_inst.get_pin("D")
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# active contact metal to poly contact metal spacing
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active_contact_to_poly_contact = bottom_pin.uy() + self.m1_space + 0.5 * contact.poly_contact.second_layer_height
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# active diffusion to poly contact spacing
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# doesn't use nmos uy because that is calculated using offset + poly height
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active_top = self.nmos1_inst.by() + self.nmos1_inst.mod.active_height
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active_to_poly_contact = active_top + self.poly_to_active + 0.5 * contact.poly_contact.first_layer_height
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active_to_poly_contact2 = active_top + drc("contact_to_gate") + 0.5 * self.route_layer_width
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self.inputA_yoffset = max(active_contact_to_poly_contact,
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active_to_poly_contact,
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active_to_poly_contact2)
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="center")
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# self.inputB_yoffset = self.inputA_yoffset + self.m3_pitch
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self.inputB_yoffset = self.output_yoffset - self.route_layer_pitch
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# This will help with the wells and the input/output placement
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self.route_input_gate(self.pmos2_inst,
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@ -189,19 +205,13 @@ class pnand2(pgate.pgate):
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self.inputB_yoffset,
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"B",
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position="center")
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="center")
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def route_output(self):
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""" Route the Z output """
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# One routing track layer below the PMOS contacts
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route_layer_offset = 0.5 * self.route_layer_width + self.route_layer_space
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output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset
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self.output_yoffset = self.pmos1_inst.get_pin("D").by() - route_layer_offset
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# PMOS1 drain
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@ -213,7 +223,7 @@ class pnand2(pgate.pgate):
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# Output pin
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out_offset = vector(nmos_pin.cx() + self.route_layer_pitch,
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output_yoffset)
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self.output_yoffset)
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# This routes on M2
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# # Midpoints of the L routes go horizontal first then vertical
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