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718 Commits

Author SHA1 Message Date
mrg e9780ea599 Add non-preferred directions for channel routes 2020-06-11 15:03:36 -07:00
mrg dff28a9997 Merge branch 'tech_migration' into dev 2020-06-10 17:09:05 -07:00
mrg bfd1abc79f Replica column pins start at 0 height. 2020-06-10 14:58:55 -07:00
mrg 157926960b Flip freepdk45 flop, dff_buf route layer change 2020-06-09 13:48:16 -07:00
mrg 77fb7017c4 Merge branch 'tech_migration' into dev 2020-06-08 12:54:41 -07:00
mrg 9cc36c6d3a Bus code converted to pins. Fix layers on control signal routes in bank. 2020-06-08 11:01:14 -07:00
Aditi Sinha 300522a1a8 Change spare enable pins offset to lower right 2020-06-08 14:31:46 +00:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 0837432d45 Wordline route layers and (optional) via. 2020-06-05 16:47:22 -07:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
mrg 00b51f5464 PEP8 format replica_bitcell_array 2020-06-05 13:49:32 -07:00
mrg 4fef632dce Fix syntax error 2020-06-05 12:13:41 -07:00
mrg a62b85a6b1 Update mirroring in port_data for bitcell mirrored arrays 2020-06-05 11:29:31 -07:00
mrg e14deff3d1 Fixed offset in port_data 2020-06-04 16:03:39 -07:00
mrg 2fcecb7227 Variable zjog. 512 port address test. s8 port address working. 2020-06-04 16:01:32 -07:00
mrg 7aafa43897 Connect RBL to bottom of precharge cell 2020-06-04 10:22:52 -07:00
mrg 249b5355ba Adjust rbl route 2020-06-03 17:08:04 -07:00
mrg 3927c62e32 Undo extra space due to nwell spacing 2020-06-03 16:39:33 -07:00
mrg 3b1fe26d25 Spacing between decoder and driver for s8 2020-06-03 14:33:30 -07:00
Joey Kunzler 6430aad857 Merge branch 'dev' into s8_update 2020-06-03 11:53:33 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
mrg 34209dac3d A port option for correct mirroring in port_data. 2020-06-02 16:50:07 -07:00
Joey Kunzler 84021c9ccb merge conflict 2 - port data 2020-06-02 16:32:08 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg fce8e878b9 Add port to col mux and simplify route with computation to fix mirror bug. 2020-06-02 13:57:41 -07:00
mrg fdf51c5a00 Add port option to precharge array 2020-06-02 11:44:22 -07:00
mrg f1b7b91b1a Use non-channel route for s8 port_data 2020-06-02 11:43:57 -07:00
mrg 45b0601e4b Fix via directions in s8 col mux 2020-06-02 11:43:31 -07:00
mrg a1c7474f80 Revert to channel route of bitlines 2020-06-02 10:08:53 -07:00
mrg b3b03d4d39 Hard cells can accept height parameter too. 2020-06-01 16:46:00 -07:00
mrg 496a24389c Remove prints 2020-05-29 16:57:47 -07:00
mrg 82dc937768 Add missing vias by using via stack function 2020-05-29 16:53:47 -07:00
Joey Kunzler b00163e4e1 lvs fix for regression tests 2020-05-29 13:50:34 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 218a553ac5 fix for replica column mirroring over y 2020-05-28 20:31:21 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Joey Kunzler 9a6b38b67e merge conflict 2020-05-26 16:03:36 -07:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha c14190c5aa Changes in control logic for spare columns 2020-05-14 10:41:54 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
mrg 4b526f0d5f Check min size inverter. 2020-05-13 16:54:26 -07:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
mrg dd73afc983 Changes to allow decoder height to be a 2x multiple of bitcell height. 
Convert to use li layer in pgates.
Fix multifinger devices with li layers.
Simplify wordline driver input routing.
Fix power pin direction option update.
PEP8 cleanup
Changes to simplify metal preferred directions and pitches.
Split of control logic tests.
 2020-05-10 06:56:22 -07:00
Aditi Sinha 5c50cf234b Fixed lvs errors for spare columns 2020-05-09 07:56:19 +00:00
Aditi Sinha e30938fb66 Spare columns working at bank level 2020-05-03 15:23:30 +00:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Joey Kunzler 1b6634bb97 port data routing fix 2020-04-29 15:48:15 -07:00
Joey Kunzler 0bae652be9 fix merge conflicts 2020-04-23 11:51:46 -07:00
Joey Kunzler fed1c0bbe1 s8 col mux array 2020-04-22 16:22:34 -07:00
mrg 32576fb62c Convert wordline driver to pand2 rather than pnand2+pdriver 2020-04-22 13:27:50 -07:00
mrg f1c1adc9bd Simplify supply contacts in delay chain. 2020-04-21 16:12:54 -07:00
mrg 0f6998a1c5 PEP8 cleanup 2020-04-21 15:36:38 -07:00
mrg cd66ddb37c Add supply rails to dff array. PEP8 cleanup. 2020-04-21 15:21:29 -07:00
mrg f6135f3471 PEP8 formatting 2020-04-20 16:38:30 -07:00
mrg 7995451cbb PEP8 formatting 2020-04-20 14:45:18 -07:00
mrg 7f65176908 Configured bitline directions into prot_data 2020-04-20 14:23:40 -07:00
mrg 843e9414df Parameterize vdd and gnd pin in write driver array. 2020-04-16 11:28:35 -07:00
mrg 770533e7b1 Parameterize vdd and gnd pin in sense amp array. 2020-04-16 11:27:26 -07:00
mrg 9d2902de9e Conditional well spacing 2020-04-15 15:55:49 -07:00
mrg e95c97d7a5 PEP8 cleanup 2020-04-15 14:29:43 -07:00
mrg 331a4f4606 Fix wire width bug in short jogs. PEP8 cleanup. 2020-04-15 09:48:42 -07:00
mrg 0941ebc3da Fix well spacing issue 2020-04-14 14:08:07 -07:00
mrg 32d190b8b1 Jog connection on M1 for bank select. 2020-04-14 12:15:56 -07:00
mrg 43dcf675a1 Move pnand outputs to M1. Debug hierarchical decoder multirow. 2020-04-14 10:52:25 -07:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg 2e67d44cd7 First pass of multiple bitcells per decoder row 2020-04-10 13:29:41 -07:00
mrg 7888e54fc4 Remove dynamic bitcell multiple detection. 
Check for decoder bitcell multiple in tech file or assume 1.
PEP8 fixes.
 2020-04-09 11:38:18 -07:00
mrg 8a55c223df Use single height for netlist_only mode 2020-04-09 09:48:54 -07:00
mrg 58fbc5351a Change rows to outputs in hierarchical decoder 2020-04-08 17:05:16 -07:00
mrg 0c27942bb2 Dynamically try and DRC decoder for height 2020-04-08 16:45:28 -07:00
Jesse Cirimelli-Low b59c789dec remove whitespace 2020-04-05 03:58:26 -07:00
Jesse Cirimelli-Low 8b33cb519f Merge branch 'dev' into custom_mod 2020-04-03 17:05:56 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
Jesse Cirimelli-Low cdf0315a90 Merge branch 'dev' into custom_mod 2020-04-01 15:35:33 -07:00
mrg 7956b63d9f Add licon option to precharge 2020-04-01 11:26:45 -07:00
mrg d916322b74 PEP8 updates 2020-03-31 10:15:46 -07:00
Joey Kunzler b0d2946c80 update to sense amp and write driver modules 2020-03-30 20:00:32 -07:00
Jesse Cirimelli-Low 341bde7a48 Merge branch 'dev' into custom_mod 2020-03-26 02:40:37 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
mrg c5a1be703c Rotate via and PEP8 formatting 2020-03-06 13:39:46 -08:00
mrg 23501c7b35 Convert pnand+pinv to pand in decoders. 2020-03-06 13:26:40 -08:00
mrg 1a2efd77ad Move rbl route away from bitcell array 2020-03-06 09:48:20 -08:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg ad98137cd4 Merge branch 'dev' into tech_migration 2020-03-05 14:18:06 -08:00
mrg 9c1f0657dd PEP8 Formatting 2020-03-05 11:58:36 -08:00
mrg 7adeef6c9e PEP8 Formatting 2020-03-05 10:21:18 -08:00
mrg 287a31f598 Precharge updates. 
Enable different layers for bitlines.
Jog bitlines to fit precharge transistors for close proximity bitlines.
PEP8 cleanup.
 2020-03-04 17:39:11 -08:00
Joey Kunzler d7529ce526 Vdd/gnd via stacks now use perferred directions, added cell property to override 2020-03-04 17:05:19 -08:00
mrg 7ba9e09e12 Incomplete precharge layer decoupling 2020-03-04 22:23:05 +00:00
Jesse Cirimelli-Low f62016ad9f revert dff_buf for no body contact 2020-03-03 12:40:08 +00:00
mrg bb2305d56a PEP8 format fixes 2020-02-28 18:24:39 +00:00
Bastian Koppelmann 0e641bf905 Remove write_driver_array.py.orig 
this was the remainder of applying a diff using "patch". To avoid this
mistake, add the filetypes created by "patch" to the .gitignore.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-21 13:29:43 +01:00
Aditi Sinha 694ea5c20e Characterization for extra rows 2020-02-20 17:31:58 +00:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
Matt Guthaus da4c69ab98 Merge branch 'pin-pull3' into dev 2020-02-20 09:07:58 -08:00
Hunter Nichols c1cb6bf512 Changed layout input names of s_en AND gate to match the schematic 2020-02-19 23:32:11 -08:00
Hunter Nichols 843fce41d7 Fixed issues with sen control logic for read ports. 2020-02-19 03:06:11 -08:00
Bastian Koppelmann 76256a2f1b sense_amp: Allow custom pin names 
we don't want to propagate the sense amp's bl/br names out of the
sense_amp_array. Thus the sense_amp_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:12 +01:00
Bastian Koppelmann 680dc6d2c7 sense_amp/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 15:20:06 +01:00
Bastian Koppelmann 9a12b68680 write_driver: Allow custom pin names 
we don't want to propagate the write driver bl/br names out of the
write_driver_array. Thus the write_driver_array gets them named as
"bl"/"br" again.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:25:00 +01:00
Bastian Koppelmann c06cb2bfc2 write_driver/array: Remove hardcoded pin names 
all pin names should be wrapped into a function/property. This ensures
that there is exactly one place to change the name.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:23:26 +01:00
Bastian Koppelmann 656fdd1008 port_data: Refactor channel_route/connect_bitlines() 
both functions share a lot of code and are passing around a lot of data
under similar names (inst1, inst1_start_bit, inst1_bl_name, ...). Thus
we group all these elements in a named tuple to ease passing around
these elements.

All callers of channel_route/connect_bitlines() either pass in the bl/br
names or rely on "br_{}"/"bl_{}" as defaults. These hard coded values
should be determined by the instances. Thus we get the bitline names
based on the instances passed in. The callers only provide a template
string, to take care of the case that bitlines are called "bl_out_{}".

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:20:03 +01:00
Bastian Koppelmann 5e1f64c8f9 modules/port_data: Add get_bl/br_name method 
if we rely on the names of the submodules (sense_amp_array,
write_driver_array, etc.) for port_data's pins, we get into trouble on
multiport SRAMs. To avoid this we use explicit names for br/bl depending
on the port number in port_data. Now each submodule does no longer need to
figure out the right name depending on the port number.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-17 14:18:32 +01:00
Bastian Koppelmann f6302caeac replica_bitcell_array: Connect bitcells based on bitcell bl/br/wl names 
this allows us to override the bl/br/wl names of each bitcell.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:37:47 +01:00
Bastian Koppelmann f9babcf666 port_data: Each submodule now specifies their bl/br names 
before the names of bl/br from the bitcell were assumed. If we want to
allow renaming of bl/br from bitcells, we have to seperate the other
modules from that. Note, that we don't touch every occurence of bl/br,
but only the once necessary that pin renaming of the bitcell works.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Bastian Koppelmann 64bf93e4e5 bank: Connect instances by their individual bl/br names 
each module should be able to state how their bl/br lines are named. Here we
always connect port_data with the bitcell_array, so port_data needs function
that return the names of bl/br.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-02-12 15:00:50 +01:00
Jesse Cirimelli-Low a23f72d5a3 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into dev 2020-02-12 06:54:03 +00:00
Jesse Cirimelli-Low aedbc5f968 merge custom cell and module properties 2020-02-12 04:09:40 +00:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
mrg 0ef06ec1e1 Fix dff_buf width in netlist_only mode 2020-02-10 20:06:34 +00:00
mrg 6bf33a980f Add conservative well spacing between library FF and our pgates. 2020-02-10 19:28:30 +00:00
jcirimel 27eced1fbe netlist_only done 2020-02-09 23:51:01 -08:00
jcirimel 7038fad930 s8 gdsless netlist only working up to pdriver 2020-02-09 23:10:33 -08:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
mrg 2ff058f5d5 PEP8 Cleanup and reverse pitch offset of col addr routing 2020-02-06 22:59:30 +00:00
mrg f0ecf385e8 Nwell fixes in pgates. 
Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.
 2020-02-06 16:20:09 +00:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
jcirimel 7cb3091140 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into custom_mod 2020-02-04 23:40:54 -08:00
jcirimel ed11145ca4 add custom module file, make dff clk pin dynamic 2020-02-04 23:35:06 -08:00
Jesse Cirimelli-Low 6cf20a0353 add technology based module customization 2020-01-30 19:44:24 +00:00
mrg 400cf0333a Pgates are 8 M1 high by default. Port data is bitcell height. 2020-01-30 03:34:04 +00:00
mrg 0880c393fd Fix base bitcell syntax error. Remove some unused imports. 2020-01-30 01:58:30 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Matt Guthaus 3147b99ce0 Merge remote-tracking branch 'bkoppelmann/bit-sym' into dev 2020-01-29 11:24:09 -08:00
Bastian Koppelmann b5701af864 column_mux: Allow y axis mirroring 
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:39 +01:00
Bastian Koppelmann ed66fca031 write_driver/sense_amp/precharge arrays: Allow y axis mirroring 
since the bitlines alternate in the bitcell array we also need to mirror
the port_data elements.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:39 +01:00
Bastian Koppelmann dd1afe0313 Bitcell arrays: Allow mirroring on the y axis 
this allows for bitcells that need to be mirrored on the y axis, like
thin cells. However, the portdata elements also need to be mirrored on
the y axis. Otherwise the router will fail horribly when connecting
bitlines.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:51:21 +01:00
Bastian Koppelmann df9f351a91 Add custom cell properties to technologies 
this is technology specific database to store data about the custom
design cells. For now it only contains on which axis the bitcells are
mirrored. This is a first step to support thin cells that need to be
mirrored on the x and y axis.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 15:46:14 +01:00
Bastian Koppelmann 90a4a72bba modules: Use add_power_pin API for all modules 
sense_amp_array, write_driver_array, and single_column_mux were the only offenders.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 11:47:49 +01:00
Bastian Koppelmann 3fb2b9c1c3 Bitcell arrays: Create abstract base class 
a lot of functions of dummy- and bitcell-array are either copy-pasted or
have just slight differences. Merge all of those into an abstract base
class such that we don't have too much duplicate code.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 10:59:58 +01:00
mrg 9beb0f4ece Add separate well design rules. 
Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
 2020-01-23 19:43:41 +00:00
Matt Guthaus 9ad06a7770 Move write mask vias to center to avoid data pins. 2019-12-20 11:48:27 -08:00
Matt Guthaus 82496a66fe Simplify supply code. 2019-12-20 10:35:57 -08:00
Matt Guthaus 9e8b03d6c2 Merge branch 'dev' into tech_migration 2019-12-19 16:23:22 -08:00
Matt Guthaus d2461e5011 Supply indexing bug resolved. Recompute width/height basted on insts. 2019-12-19 16:19:21 -08:00
Bastian Koppelmann 1df16eceb6 sram_factory: Give proper priority to overrides 
modules overridden by the user are the highest priority, then modules
overridden by the technology. If nothing is overriden, use the defaults
from OPTS (if they exist) or use the requested module_type.

This fixes that custom tech_modules could not be used, if they had a default in
OPTS even if the latter was not overridden by the user.

We don't need extra defaults in the tech_modules, as we now only use them,
if they have been overridden by the tech_module.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-19 15:58:00 +01:00
Bastian Koppelmann fab963701b sram_base: Instantiate "dff_array" and "bank" through sram_factory 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:50 +01:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus f30d0b9197 Fix KeyError for bitell types. 2019-12-16 12:04:33 -08:00
Bastian Koppelmann 233ec010ff modules: Create a class that wraps all the module class names 
this removes hard coded values from the module instatiations. It also allows
users to override certain modules with their custom cells.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-16 16:51:38 +01:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Aditi Sinha 5b3846e1e5 Changed replica bitcell array to work with bank tests for non power of two rows 2019-12-08 13:24:39 +00:00
Matthew Guthaus b3b3cf0210 Merge remote-tracking branch 'origin/dev' into tech_migration 2019-11-17 00:15:18 +00:00
Aditi Sinha 2c7aa5d0da Non-power of 2 address decode tentative 2019-11-15 03:59:57 +00:00
Matthew Guthaus 131f4bda4a Add layer-purpose GDS support. Various PEP8 fixes. 2019-11-14 18:17:20 +00:00
Matthew Guthaus a2422cc8d4 Sometimes round down pdriver to fix polarity 2019-11-06 21:51:21 +00:00