mirror of https://github.com/VLSIDA/OpenRAM.git
Supply indexing bug resolved. Recompute width/height basted on insts.
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@ -42,6 +42,10 @@ class bank_select(design.design):
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self.place_instances()
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self.route_instances()
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self.height = max([x.uy() for x in self.inv_inst]) + self.m1_width
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self.width = max([x.rx() for x in self.inv_inst])
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self.add_boundary()
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self.DRC_LVS()
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@ -96,14 +100,11 @@ class bank_select(design.design):
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self.xoffset_nand = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_nor = self.inv4x.width + 2*self.m2_pitch + drc("pwell_to_nwell")
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self.xoffset_inv = max(self.xoffset_nand + self.nand2.width, self.xoffset_nor + self.nor2.width)
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self.xoffset_bank_sel_inv = 0
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self.xoffset_inputs = 0
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self.yoffset_maxpoint = self.num_control_lines * self.inv4x.height
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# Include the M1 pitches for the supply rails and spacing
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self.height = self.yoffset_maxpoint + 2*self.m1_pitch
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self.width = self.xoffset_inv + self.inv4x.width
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def create_instances(self):
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@ -197,7 +198,7 @@ class bank_select(design.design):
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mirror=mirror)
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# They all get inverters on the output
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inv_inst.place(offset=[self.xoffset_inv, y_offset],
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inv_inst.place(offset=[logic_inst.rx(), y_offset],
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mirror=mirror)
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@ -312,14 +313,14 @@ class bank_select(design.design):
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offset=pin_pos)
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# Add vdd/gnd supply rails
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gnd_pin = inv_inst.get_pin("gnd")
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gnd_pin = self.inv_inst[num].get_pin("gnd")
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left_gnd_pos = vector(0, gnd_pin.cy())
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self.add_layout_pin_segment_center(text="gnd",
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layer="m1",
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start=left_gnd_pos,
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end=gnd_pin.rc())
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vdd_pin = inv_inst.get_pin("vdd")
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vdd_pin = self.inv_inst[num].get_pin("vdd")
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left_vdd_pos = vector(0, vdd_pin.cy())
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self.add_layout_pin_segment_center(text="vdd",
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layer="m1",
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