mirror of https://github.com/VLSIDA/OpenRAM.git
s8 gdsless netlist only working up to pdriver
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parent
b212b3e85a
commit
7038fad930
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@ -13,17 +13,44 @@ class _dff:
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self.custom_type_list = custom_type_list
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self.clk_pin = clk_pin
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class _dff_buff:
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def __init__(self, use_custom_ports, custom_buff_ports, add_body_contacts):
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self.use_custom_ports = use_custom_ports
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self.buf_ports = custom_buff_ports
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self.add_body_contacts = add_body_contacts
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class _dff_buff_array:
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def __init__(self, use_custom_ports, add_body_contacts):
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self.use_custom_ports = use_custom_ports
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self.add_body_contacts = add_body_contacts
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class module_properties():
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"""
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TODO
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"""
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def __init__(self):
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self.names = {}
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self._dff = _dff(use_custom_ports = False,
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custom_port_list = ["D", "Q", "clk", "vdd", "gnd"],
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custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
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clk_pin= "clk")
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self._dff_buff = _dff_buff(use_custom_ports = False,
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custom_buff_ports = ["D", "qint", "clk", "vdd", "gnd"],
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add_body_contacts = False)
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self._dff_buff_array = _dff_buff_array(use_custom_ports = False,
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add_body_contacts = False)
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@property
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def dff(self):
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return self._dff
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@property
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def dff_buff(self):
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return self._dff_buff
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@property
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def dff_buff_array(self):
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return self._dff_buff_array
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@ -7,7 +7,7 @@
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#
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import debug
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import design
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from tech import drc,parameter
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from tech import drc,parameter,module_properties
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from math import log
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from vector import vector
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from globals import OPTS
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@ -82,10 +82,15 @@ class dff_buf(design.design):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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if module_properties.dff_buff.add_body_contacts:
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self.add_pin("vpb", "INPUT")
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self.add_pin("vpn", "INPUT")
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def create_instances(self):
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self.dff_inst=self.add_inst(name="dff_buf_dff",
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mod=self.dff)
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self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
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self.connect_inst(module_properties.dff_buff.buf_ports)
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#self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
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self.inv1_inst=self.add_inst(name="dff_buf_inv1",
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mod=self.inv1)
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@ -7,7 +7,7 @@
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#
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import debug
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import design
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from tech import drc
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from tech import drc, module_properties
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from math import log
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from vector import vector
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from globals import OPTS
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@ -64,6 +64,10 @@ class dff_buf_array(design.design):
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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if module_properties.dff_buff_array.add_body_contacts:
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self.add_pin("vpb", "INPUT")
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self.add_pin("vnb", "INPUT")
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def add_modules(self):
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self.dff = factory.create(module_type="dff_buf",
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inv1_size=self.inv1_size,
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@ -77,12 +81,16 @@ class dff_buf_array(design.design):
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name = "dff_r{0}_c{1}".format(row,col)
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self.dff_insts[row,col]=self.add_inst(name=name,
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mod=self.dff)
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self.connect_inst([self.get_din_name(row,col),
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inst_ports = [self.get_din_name(row,col),
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self.get_dout_name(row,col),
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self.get_dout_bar_name(row,col),
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"clk",
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"vdd",
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"gnd"])
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"gnd"]
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if module_properties.dff_buff_array.add_body_contacts:
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inst_ports.append("vpb")
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inst_ports.append("vnb")
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self.connect_inst(inst_ports)
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def place_dff_array(self):
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for row in range(self.rows):
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