mirror of https://github.com/VLSIDA/OpenRAM.git
add simple sram sizing for netlist only
This commit is contained in:
parent
18573c0e42
commit
3a06141030
|
|
@ -96,8 +96,10 @@ def get_libcell_size(name, units, lpp):
|
|||
Open a GDS file and return the library cell size from either the
|
||||
bounding box or a border layer.
|
||||
"""
|
||||
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
|
||||
return(get_gds_size(name, cell_gds, units, lpp))
|
||||
if not OPTS.netlist_only:
|
||||
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
|
||||
return(get_gds_size(name, cell_gds, units, lpp))
|
||||
return (0,0,)
|
||||
|
||||
|
||||
def get_gds_pins(pin_names, name, gds_filename, units):
|
||||
|
|
@ -128,8 +130,11 @@ def get_libcell_pins(pin_list, name, units):
|
|||
Open a GDS file and find the pins in pin_list as text on a given layer.
|
||||
Return these as a rectangle layer pair for each pin.
|
||||
"""
|
||||
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
|
||||
return(get_gds_pins(pin_list, name, cell_gds, units))
|
||||
if not OPTS.netlist_only:
|
||||
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
|
||||
return(get_gds_pins(pin_list, name, cell_gds, units))
|
||||
else:
|
||||
return
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -57,6 +57,7 @@ class bank(design.design):
|
|||
|
||||
|
||||
def create_netlist(self):
|
||||
|
||||
self.compute_sizes()
|
||||
self.add_modules()
|
||||
self.add_pins() # Must create the replica bitcell array first
|
||||
|
|
|
|||
|
|
@ -23,9 +23,12 @@ class sram_config:
|
|||
# This will get over-written when we determine the organization
|
||||
self.words_per_row = words_per_row
|
||||
|
||||
if not OPTS.netlist_only:
|
||||
self.compute_sizes()
|
||||
else:
|
||||
self.compute_simple_sram_sizes()
|
||||
|
||||
self.compute_sizes()
|
||||
|
||||
|
||||
|
||||
def set_local_config(self, module):
|
||||
""" Copy all of the member variables to the given module for convenience """
|
||||
|
|
@ -35,6 +38,14 @@ class sram_config:
|
|||
# Copy all the variables to the local module
|
||||
for member in members:
|
||||
setattr(module,member,getattr(self,member))
|
||||
def compute_simple_sram_sizes(self):
|
||||
self.row_addr_size = int(log(OPTS.num_words, 2))
|
||||
self.col_addr_size = int(log(OPTS.word_size, 2))
|
||||
self.words_per_row = 1
|
||||
self.num_rows = OPTS.num_words
|
||||
self.num_cols = OPTS.word_size
|
||||
self.bank_addr_size = self.col_addr_size + self.row_addr_size
|
||||
self.addr_size = self.bank_addr_size + int(log(self.num_banks, 2))
|
||||
|
||||
def compute_sizes(self):
|
||||
""" Computes the organization of the memory using bitcell size by trying to make it square."""
|
||||
|
|
|
|||
Loading…
Reference in New Issue