mirror of https://github.com/VLSIDA/OpenRAM.git
modules: Use add_power_pin API for all modules
sense_amp_array, write_driver_array, and single_column_mux were the only offenders. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -98,18 +98,15 @@ class sense_amp_array(design.design):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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gnd_pos = inst.get_pin("gnd").center()
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self.add_via_center(layers=self.m2_stack,
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offset=gnd_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="m3",
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offset=gnd_pos)
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vdd_pos = inst.get_pin("vdd").center()
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self.add_via_center(layers=self.m2_stack,
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offset=vdd_pos)
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self.add_layout_pin_rect_center(text="vdd",
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layer="m3",
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offset=vdd_pos)
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self.add_power_pin(name = "gnd",
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loc = inst.get_pin("gnd").center(),
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start_layer="m2",
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vertical=True)
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self.add_power_pin(name = "vdd",
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loc = inst.get_pin("vdd").center(),
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start_layer="m2",
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vertical=True)
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bl_pin = inst.get_pin("bl")
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br_pin = inst.get_pin("br")
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@ -141,13 +141,10 @@ class write_driver_array(design.design):
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for n in ["vdd", "gnd"]:
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pin_list = self.driver_insts[i].get_pins(n)
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for pin in pin_list:
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pin_pos = pin.center()
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# Add the M2->M3 stack
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self.add_via_center(layers=self.m2_stack,
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offset=pin_pos)
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self.add_layout_pin_rect_center(text=n,
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layer="m3",
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offset=pin_pos)
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self.add_power_pin(name = n,
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loc = pin.center(),
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vertical=True,
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start_layer = "m2")
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if self.write_size:
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for bit in range(self.num_wmasks):
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en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
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@ -180,14 +180,10 @@ class single_level_column_mux(pgate.pgate):
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implant_type="p",
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well_type="p")
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# Add the M1->M2->M3 stack
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self.add_via_center(layers=self.m1_stack,
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offset=active_pos)
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self.add_via_center(layers=self.m2_stack,
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offset=active_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="m3",
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offset=active_pos)
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# Add the M1->..->power_grid_layer stack
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self.add_power_pin(name = "gnd",
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loc = active_pos,
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start_layer="m1")
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# Add well enclosure over all the tx and contact
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self.add_rect(layer="pwell",
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