mirror of https://github.com/VLSIDA/OpenRAM.git
Simplify supply code.
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9e8b03d6c2
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@ -104,8 +104,6 @@ class write_mask_and_array(design.design):
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def add_layout_pins(self):
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self.nand2 = factory.create(module_type="pnand2")
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supply_pin=self.nand2.get_pin("vdd")
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# Create the enable pin that connects all write mask AND array's B pins
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beg_en_pin = self.and2_insts[0].get_pin("B")
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@ -139,15 +137,16 @@ class write_mask_and_array(design.design):
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self.add_via_center(layers=self.m2_stack,
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offset=en_pin.center())
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self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))
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self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height))
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# Route power and ground rails together
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if i < self.num_wmasks-1:
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for n in ["gnd","vdd"]:
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pin = self.and2_insts[i].get_pin(n)
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next_pin = self.and2_insts[i+1].get_pin(n)
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self.add_path("m1",[pin.center(),next_pin.center()])
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for supply in ["gnd", "vdd"]:
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supply_pin=self.and2_insts[i].get_pin(supply)
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self.add_power_pin(supply, supply_pin.rc())
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for supply in ["gnd", "vdd"]:
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supply_pin_left = self.and2_insts[0].get_pin(supply)
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supply_pin_right = self.and2_insts[self.num_wmasks-1].get_pin(supply)
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self.add_path("m1",[supply_pin_left.lc(), supply_pin_right.rc()])
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def get_cin(self):
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"""Get the relative capacitance of all the input connections in the bank"""
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# The enable is connected to an and2 for every row.
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