mirror of https://github.com/VLSIDA/OpenRAM.git
write_driver/sense_amp/precharge arrays: Allow y axis mirroring
since the bitlines alternate in the bitcell array we also need to mirror the port_data elements. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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@ -107,9 +107,19 @@ class precharge_array(design.design):
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def place_insts(self):
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""" Places precharge array by horizontally tiling the precharge cell"""
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from tech import cell_properties
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xoffset = 0
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for i in range(self.columns):
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offset = vector(self.pc_cell.width * i, 0)
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self.local_insts[i].place(offset)
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tempx = xoffset
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if cell_properties.bitcell.mirror.y and (i + 1) % 2:
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mirror = "MY"
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tempx = tempx + self.pc_cell.width
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else:
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mirror = ""
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offset = vector(tempx, 0)
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self.local_insts[i].place(offset=offset, mirror=mirror)
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xoffset = xoffset + self.pc_cell.width
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def get_en_cin(self):
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"""Get the relative capacitance of all the clk connections in the precharge array"""
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@ -84,14 +84,27 @@ class sense_amp_array(design.design):
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"en", "vdd", "gnd"])
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def place_sense_amp_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.amp.width:
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amp_spacing = self.bitcell.width * self.words_per_row
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else:
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amp_spacing = self.amp.width * self.words_per_row
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for i in range(0,self.word_size):
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amp_position = vector(amp_spacing * i, 0)
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self.local_insts[i].place(amp_position)
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xoffset = amp_spacing * i
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# align the xoffset to the grid of bitcells. This way we
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# know when to do the mirroring.
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grid_x = int(xoffset / self.amp.width)
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if cell_properties.bitcell.mirror.y and grid_x % 2:
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mirror = "MY"
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xoffset = xoffset + self.amp.width
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else:
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mirror = ""
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amp_position = vector(xoffset, 0)
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self.local_insts[i].place(offset=amp_position,mirror=mirror)
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def add_layout_pins(self):
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@ -106,14 +106,23 @@ class write_driver_array(design.design):
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def place_write_array(self):
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from tech import cell_properties
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if self.bitcell.width > self.driver.width:
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self.driver_spacing = self.bitcell.width
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else:
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self.driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
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index = int(i/self.words_per_row)
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base = vector(i * self.driver_spacing, 0)
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self.driver_insts[index].place(base)
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xoffset = i * self.driver_spacing
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if cell_properties.bitcell.mirror.y and i % 2:
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mirror = "MY"
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xoffset = xoffset + self.driver.width
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else:
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mirror = ""
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base = vector(xoffset, 0)
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self.driver_insts[index].place(offset=base, mirror=mirror)
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def add_layout_pins(self):
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