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OpenRAM
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262 Commits

Author SHA1 Message Date
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 8e8a97cc4b Add correct boundary to SRAM 2020-06-14 14:17:35 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
jcirimel 0f9e38881c update stim for large pex layouts 2020-05-04 03:05:33 -07:00
jcirimel 89688f8ea9 fix pex for larger memories 2020-05-04 01:31:51 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg c8c74e8b69 Fix lvs_write in sram class 2020-04-06 15:20:59 -07:00
mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) 2020-04-03 13:39:54 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 9106e22b58 Fix typo and syntax error. 2020-04-02 10:37:21 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg 05f9e809b4 PEP8 Formatting 2020-03-05 16:27:35 -08:00
mrg 6506622dfb PEP8 Formatting 2020-03-05 16:20:21 -08:00
mrg 5b23653369 PEP8 Formatting 2020-03-05 16:13:49 -08:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
mrg 4d85640a00 Change col addr spacing to col addr size 2020-02-07 22:20:16 +00:00
mrg 2ff058f5d5 PEP8 Cleanup and reverse pitch offset of col addr routing 2020-02-06 22:59:30 +00:00
mrg 4b06ab9eaf Move port 2 column address bus down. 
PEP 8 cleanup.
 2020-02-06 19:46:10 +00:00
Jesse Cirimelli-Low b107934672 fix styling 2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Bastian Koppelmann 9749c522d1 tech: Make power_grid configurable 
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.

For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:34 +01:00
Jesse Cirimelli-Low 6e070925b6 update magic for multiport 2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low 30604fb093 add multiport support for pex labels 2020-01-28 00:28:55 +00:00
Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell 2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low d42cd9a281 pbitcell working with bitline adjustments 2020-01-27 10:03:31 +00:00
Jesse Cirimelli-Low 1062cbfd7f begin fixes to pbitcell, prepare multibank pex 2020-01-24 10:24:29 +00:00
jcirimel 40c01dab85 fix bl in stim file 2020-01-21 01:44:15 -08:00
jcirimel 73691f6054 fix bug in top level bitline label placement 2020-01-21 00:20:52 -08:00
Jesse Cirimelli-Low 5778901cfe pull bitline labels to top level spice 2020-01-20 12:16:30 +00:00
jcirimel 364842569a fix s_en in stim 2020-01-16 12:16:49 -08:00
jcirimel 075bf0d841 label bitcell in stim, add s_en top level to stim 2020-01-16 03:51:29 -08:00
Jesse Cirimelli-Low 3ab99d7f9c update gds library, generalize geometry reverse transform function 2019-12-24 05:01:55 +00:00
Bastian Koppelmann fab963701b sram_base: Instantiate "dff_array" and "bank" through sram_factory 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:50 +01:00
Jesse Cirimelli-Low 88d3da0b4a fix control logic pex labels with multiport 2019-12-18 12:45:12 +00:00
jcirimel f0958b0b11 squashed update of pex progress due to timezone error 2019-12-18 03:03:13 -08:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Aditi Sinha 5b3846e1e5 Changed replica bitcell array to work with bank tests for non power of two rows 2019-12-08 13:24:39 +00:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
jsowash 8c33749223 Uncommented offset_all_coordinates. 2019-09-04 16:41:27 -07:00
jsowash febc053587 Moved SRAM macro in LEF file to origin and removed poly. 2019-09-04 16:11:12 -07:00
jsowash fbecb9bc02 Added poly to LEF files. 2019-09-04 14:06:17 -07:00
jsowash d6e7047e2f Added metal4 to lef files since it's now used with a wmask. 2019-09-04 13:04:51 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash e3b42430bd Changed max_gap_size_wmask to take into account column ffs. 2019-08-29 17:09:17 -07:00
jsowash bbe235074c Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing. 2019-08-29 16:41:58 -07:00
jsowash 37116ce9d8 Increased spacing between wmask and data dffs. 2019-08-29 16:00:50 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash af3d2af0ec Merge branch 'dev' into add_wmask 2019-08-29 12:56:11 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
jsowash 737e873923 Changed via direction for via1 in flip flops. 2019-08-21 14:49:54 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
jsowash 980760b724 Add preferred direction to via1, routed between supply lines in wmask AND array, and only uses m3 for channel route with a write mask. 2019-08-21 14:02:57 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
jsowash 4f01eeb3c1 Combined changes to the pin locations and vias. 2019-08-21 12:36:53 -07:00
jsowash c2015335b0 Fixed merge issues. 2019-08-21 11:54:22 -07:00
jsowash 4813c01d56 Moved dff's up and moved wmask_AND/wdriver pins left/down, respectively. 2019-08-21 11:50:28 -07:00
Matt Guthaus b94af3e3fd Add vias for new channel routes 2019-08-21 11:33:43 -07:00
jsowash 0cbc4a7acf Moved wmask dff above data dff and changed channel route to m3/m4 for data and m1/m2 for wmask. 2019-08-21 10:07:20 -07:00
jsowash c19bada8df Performed clean up and added comments. 2019-08-19 08:57:05 -07:00
jsowash f0f811bad9 Added a condiitonal to only route wmask dff when there's a write size. 2019-08-14 12:40:14 -07:00
jsowash 858fbb062d Placed wmask dff and added connections for wmask pins. 2019-08-14 11:45:22 -07:00
jsowash 0d7170eb95 Created wmask AND array en pin to go through to top layer. 2019-08-14 09:59:40 -07:00
Matt Guthaus 8d6a4c74e7 Merge branch 'dev' into control_fix 2019-08-10 13:07:30 -07:00
Matt Guthaus 23676c0f37 Route bl in SRAM write ports too 2019-08-10 12:53:07 -07:00
Hunter Nichols d273c0eef5 Merge branch 'dev' into analytical_cleanup 2019-08-08 13:20:27 -07:00
Hunter Nichols 3c44ce2df6 Replaced analytical characterization with graph implementation. Removed most analytical delay functions used by old chacterizer. 2019-08-08 02:33:51 -07:00
Matt Guthaus d36f14b408 New control logic, netlist only working 2019-08-07 17:14:33 -07:00
Matt Guthaus a2f81aeae4 Combine rbl_wl and wl_en. Size p_en_bar slower than wl_en. 2019-08-06 16:29:07 -07:00
Matt Guthaus 4d11de64ac Additional debug. Smaller psram func tests. 2019-08-05 13:53:14 -07:00
Matt Guthaus ff64e7663e Add p_en_bar to write ports as well 2019-08-01 12:21:43 -07:00
Matt Guthaus 2824315f79 Fix error in wmask if 2019-07-27 11:51:40 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
jsowash 0a5461201a Change num_wmask to num_wmasks and write_size = None not word_size if wmask not used. 2019-07-19 14:58:37 -07:00
jsowash 45cb159d7f Connected wmask in the spice netlist. 2019-07-19 13:17:55 -07:00
mrg bea07c2319 SRAM with RBL integration in array. 2019-07-16 09:04:58 -07:00
jsowash 021d604832 Removed wmask from addwrite() 2019-07-15 16:48:36 -07:00
jsowash ea2f786dcf Redefined write_size inrecompute_sizes() to take the new word_size() 2019-07-15 14:41:26 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
jsowash dfa2b29b8f Begin adding wmask netlist and spice tests. 2019-07-12 10:34:29 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg b841fd7ce3 Replica bitcell array with arbitrary RBLs working 2019-07-10 15:56:51 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash f29631695c Finished merge 2019-07-05 11:43:31 -07:00
jsowash 150259e2ba Added write_size to control_logic_r parameters. 2019-07-05 11:40:02 -07:00
mrg dd62269e0b Some cleanup 2019-07-05 08:18:58 -07:00
jsowash 02a0cd71ac fixed merge conflict 2019-07-04 11:14:32 -07:00
jsowash 125112b562 Added wmask flip flop. Need work on placement still. 2019-07-04 10:34:14 -07:00
mrg 8b0b2e2817 Merge branch 'dev' into rbl_revamp 2019-07-03 14:05:28 -07:00