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fix bug in top level bitline label placement

This commit is contained in:
jcirimel 2020-01-21 00:20:52 -08:00
parent 5778901cfe
commit 73691f6054
5 changed files with 18 additions and 5 deletions
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8
compiler/bitcells/bitcell_base.py
View File

@ -101,11 +101,15 @@ class bitcell_base(design.design):
def get_bitline_offset(self):
self.bitline_names = ["bl", "br"]
found_bitlines = []
self.bitline_offsets = []
for i in range(len(self.bitline_names)):
for text in self.gds.getTexts(layer["metal2"]):
if self.bitline_names[i] == text.textString.rstrip('\x00'):
self.bitline_offsets.append(text.coordinates[0])
if not self.bitline_names[i] in found_bitlines:
if self.bitline_names[i] == text.textString.rstrip('\x00'):
self.bitline_offsets.append(text.coordinates[0])
found_bitlines.append(self.bitline_names[i])
continue
for i in range(len(self.bitline_offsets)):
self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]])

5
compiler/characterizer/delay.py
View File

@ -302,7 +302,10 @@ class delay(simulation):
exclude_set = self.get_bl_name_search_exclusions()
for int_net in [cell_bl, cell_br]:
bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
#if OPTS.use_pex:
# bank_num = 0
# bl_names[0] = "bl_b{0}_{1}".format(bank_num, )
# bl_names[1] = "br_b{0}_{1}".format(bank_num, )
return bl_names[0], bl_names[1]

3
compiler/characterizer/stimuli.py
View File

@ -57,6 +57,9 @@ class stimuli():
for col in range(OPTS.word_size):
self.sf.write("bitcell_Q_b{0}_r{1}_c{2} ".format(bank,row,col))
self.sf.write("bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank,row,col))
for col in range(OPTS.word_size):
self.sf.write("bl_b{0}_c{2} ".format(bank, row,col))
self.sf.write("br_b{0}_c{2} ".format(bank, row,col))
self.sf.write("s_en{0} ".format(bank))
self.sf.write("{0}\n".format(model_name))

4
compiler/sram/sram_base.py
View File

@ -115,8 +115,8 @@ class sram_base(design, verilog, lef):
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
self.add_layout_pin_rect_center("bitcell_bl_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("bitcell_br_b{0}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
self.add_layout_pin_rect_center("bl_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br_b{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)

3
compiler/verify/magic.py
View File

@ -419,6 +419,9 @@ def correct_port(name, output_file_name, ref_file_name):
for col in range(OPTS.word_size):
bitcell_list += "bitcell_Q_b{0}_r{1}_c{2} ".format(bank, row,col)
bitcell_list += "bitcell_Q_bar_b{0}_r{1}_c{2} ".format(bank, row,col)
for col in range(OPTS.word_size):
bitcell_list += "bl_b{0}_c{2} ".format(bank, row,col)
bitcell_list += "br_b{0}_c{2} ".format(bank, row,col)
bitcell_list += "\n"
control_list = "+ "