mirror of https://github.com/VLSIDA/OpenRAM.git
Starting to implement minimizing channel router (not done)
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mrg
parent
c7bc01c3a9
commit
ba3d32fa0c
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@ -12,6 +12,69 @@ from vector import vector
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import design
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class channel_net():
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def __init__(self, net_name, pins, vertical):
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self.name = net_name
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self.pins = pins
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self.vertical = vertical
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# Keep track of the internval
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if vertical:
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self.min_value = min(i.by() for i in pins)
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self.max_value = max(i.uy() for i in pins)
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else:
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self.min_value = min(i.lx() for i in pins)
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self.max_value = max(i.rx() for i in pins)
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# Keep track of the conflicts
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self.conflicts = []
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def __str__(self):
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return self.name
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def __repr__(self):
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return self.name
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def __lt__(self, other):
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return self.min_value < other.min_value
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def vcg_pin_overlap(self, pin1, pin2, pitch):
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""" Check for vertical or horizontal overlap of the two pins """
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# FIXME: If the pins are not in a row, this may break.
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# However, a top pin shouldn't overlap another top pin,
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# for example, so the extra comparison *shouldn't* matter.
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# Pin 1 must be in the "BOTTOM" set
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x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch
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# Pin 1 must be in the "LEFT" set
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y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch
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overlaps = (not self.vertical and x_overlap) or (self.vertical and y_overlap)
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return overlaps
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def vcg_nets_overlap(self, other, pitch):
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"""
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Check all the pin pairs on two nets and return a pin
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overlap if any pin overlaps.
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"""
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for pin1 in self.pins:
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for pin2 in other.pins:
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if self.vcg_pin_overlap(pin1, pin2, pitch):
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return True
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return False
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def hcg_nets_overlap(self, other):
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"""
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Check if the horizontal span of the two nets overlaps eachother.
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"""
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min_overlap = self.min_value >= other.min_value and self.min_value <= other.max_value
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max_overlap = self.max_value >= other.min_value and self.max_value <= other.max_value
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return min_overlap or max_overlap
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class channel_route(design.design):
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unique_id = 0
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@ -86,104 +149,112 @@ class channel_route(design.design):
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# FIXME: This is O(n^2), so maybe optimize it.
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for other_pin, conflicts in g.items():
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if pin in conflicts:
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conflicts.remove(pin)
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g[other_pin]=conflicts
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g[other_pin].remove(pin)
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return g
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def route(self):
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# Create names for the nets for the graphs
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nets = []
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index = 0
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# print(self.netlist)
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for pin_list in self.netlist:
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nets.append(channel_net("n{}".format(index), pin_list, self.vertical))
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index += 1
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def vcg_nets_overlap(self, net1, net2):
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"""
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Check all the pin pairs on two nets and return a pin
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overlap if any pin overlaps.
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"""
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# Create the (undirected) horizontal constraint graph
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hcg = collections.OrderedDict()
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for net1 in nets:
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for net2 in nets:
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if net1.name == net2.name:
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continue
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if net1.hcg_nets_overlap(net2):
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try:
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hcg[net1.name].append(net2.name)
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except KeyError:
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hcg[net1.name] = [net2.name]
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try:
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hcg[net2.name].append(net1.name)
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except KeyError:
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hcg[net2.name] = [net1.name]
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# Initialize the vertical conflict graph (vcg)
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# and make a list of all pins
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vcg = collections.OrderedDict()
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# print("Nets:")
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# for net_name in nets:
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# print(net_name, [x.name for x in nets[net_name]])
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# Find the vertical pin conflicts
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# FIXME: O(n^2) but who cares for now
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if self.vertical:
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pitch = self.horizontal_nonpref_pitch
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else:
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pitch = self.vertical_nonpref_pitch
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for pin1 in net1:
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for pin2 in net2:
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if self.vcg_pin_overlap(pin1, pin2, pitch):
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return True
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for net in nets:
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vcg[net.name] = []
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return False
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def route(self):
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# FIXME: Must extend this to a horizontal conflict graph
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# too if we want to minimize the
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# number of tracks!
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# hcg = {}
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# Initialize the vertical conflict graph (vcg)
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# and make a list of all pins
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vcg = collections.OrderedDict()
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# Create names for the nets for the graphs
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nets = collections.OrderedDict()
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index = 0
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# print(netlist)
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for pin_list in self.netlist:
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net_name = "n{}".format(index)
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index += 1
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nets[net_name] = pin_list
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# print("Nets:")
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# for net_name in nets:
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# print(net_name, [x.name for x in nets[net_name]])
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# Find the vertical pin conflicts
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# FIXME: O(n^2) but who cares for now
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for net_name1 in nets:
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if net_name1 not in vcg.keys():
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vcg[net_name1] = []
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for net_name2 in nets:
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if net_name2 not in vcg.keys():
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vcg[net_name2] = []
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for net1 in nets:
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for net2 in nets:
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# Skip yourself
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if net_name1 == net_name2:
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if net1.name == net2.name:
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continue
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if self.vcg_nets_overlap(nets[net_name1],
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nets[net_name2]):
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vcg[net_name2].append(net_name1)
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if net1.vcg_nets_overlap(net2, pitch):
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vcg[net2.name].append(net1.name)
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current_offset = self.offset
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# list of routes to do
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while vcg:
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# Sort nets by left edge value
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nets.sort()
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while len(nets) > 0:
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current_offset_value = current_offset.y if self.vertical else current_offset.x
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# from pprint import pformat
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# print("VCG:\n", pformat(vcg))
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# for name,net in vcg.items():
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# print(name, net.min_value, net.max_value, net.conflicts)
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# print(current_offset)
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# get a route from conflict graph with empty fanout set
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net_name = None
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for net_name, conflicts in vcg.items():
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if len(conflicts) == 0:
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vcg = self.remove_net_from_graph(net_name, vcg)
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for net in nets:
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# If it has no conflicts and the interval is to the right of the current offset in the track
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if net.min_value > current_offset_value and len(vcg[net.name]) == 0:
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# print("Routing {}".format(net.name))
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# Add the trunk routes from the bottom up for
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# horizontal or the left to right for vertical
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if self.vertical:
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self.add_vertical_trunk_route(net.pins,
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current_offset,
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self.vertical_nonpref_pitch)
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current_offset = vector(current_offset.x, net.max_value + self.horizontal_nonpref_pitch)
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else:
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self.add_horizontal_trunk_route(net.pins,
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current_offset,
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self.horizontal_nonpref_pitch)
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current_offset = vector(net.max_value + self.vertical_nonpref_pitch, current_offset.y)
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# Remove the net from other constriants in the VCG
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vcg = self.remove_net_from_graph(net.name, vcg)
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nets.remove(net)
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break
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else:
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# FIXME: We don't support cyclic VCGs right now.
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debug.error("Cyclic VCG in channel router.", -1)
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# These are the pins we'll have to connect
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pin_list = nets[net_name]
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# print("Routing:", net_name, [x.name for x in pin_list])
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# Remove the net from other constriants in the VCG
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vcg = self.remove_net_from_graph(net_name, vcg)
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# Add the trunk routes from the bottom up for
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# horizontal or the left to right for vertical
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if self.vertical:
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self.add_vertical_trunk_route(pin_list,
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current_offset,
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self.vertical_nonpref_pitch)
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# This accounts for the via-to-via spacings
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current_offset += vector(self.horizontal_nonpref_pitch, 0)
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else:
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self.add_horizontal_trunk_route(pin_list,
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current_offset,
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self.horizontal_nonpref_pitch)
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# This accounts for the via-to-via spacings
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current_offset += vector(0, self.vertical_nonpref_pitch)
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# If we made a full pass and the offset didn't change...
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current_offset_value = current_offset.y if self.vertical else current_offset.x
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initial_offset_value = self.offset.y if self.vertical else self.offset.x
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if current_offset_value == initial_offset_value:
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# FIXME: We don't support cyclic VCGs right now.
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debug.error("Cyclic VCG in channel router.", -1)
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# Increment the track and reset the offset to the start (like a typewriter)
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if self.vertical:
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current_offset = vector(current_offset.x + self.horizontal_nonpref_pitch, self.offset.y)
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else:
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current_offset = vector(self.offset.x, current_offset.y + self.vertical_nonpref_pitch)
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# Return the size of the channel
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if self.vertical:
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self.width = 0
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@ -226,6 +297,17 @@ class channel_route(design.design):
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self.add_path(self.vertical_layer,
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[vector(min_x - half_layer_width, trunk_offset.y),
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vector(max_x + half_layer_width, trunk_offset.y)])
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# Route each pin to the trunk
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for pin in pins:
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if pin.cy() < trunk_offset.y:
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pin_pos = pin.uc()
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else:
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pin_pos = pin.bc()
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# No bend needed here
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mid = vector(pin_pos.x, trunk_offset.y)
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self.add_path(self.vertical_layer, [pin_pos, mid])
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else:
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# Add the horizontal trunk
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self.add_path(self.horizontal_layer,
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@ -269,6 +351,17 @@ class channel_route(design.design):
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self.add_path(self.horizontal_layer,
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[vector(trunk_offset.x, min_y - half_layer_width),
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vector(trunk_offset.x, max_y + half_layer_width)])
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# Route each pin to the trunk
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for pin in pins:
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# Find the correct side of the pin
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if pin.cx() < trunk_offset.x:
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pin_pos = pin.rc()
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else:
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pin_pos = pin.lc()
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# No bend needed here
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mid = vector(trunk_offset.x, pin_pos.y)
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self.add_path(self.horizontal_layer, [pin_pos, mid])
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else:
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# Add the vertical trunk
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self.add_path(self.vertical_layer,
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@ -292,18 +385,4 @@ class channel_route(design.design):
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to_layer=self.horizontal_layer,
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offset=pin_pos)
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def vcg_pin_overlap(self, pin1, pin2, pitch):
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""" Check for vertical or horizontal overlap of the two pins """
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# FIXME: If the pins are not in a row, this may break.
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# However, a top pin shouldn't overlap another top pin,
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# for example, so the extra comparison *shouldn't* matter.
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# Pin 1 must be in the "BOTTOM" set
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x_overlap = pin1.by() < pin2.by() and abs(pin1.center().x - pin2.center().x) < pitch
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# Pin 1 must be in the "LEFT" set
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y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y - pin2.center().y) < pitch
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overlaps = (not self.vertical and x_overlap) or (self.vertical and y_overlap)
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return overlaps
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@ -384,6 +384,14 @@ class sram_1bank(sram_base):
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, sram_pins)))
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# spare wen dff
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if self.num_spare_cols > 0 and port in self.write_ports:
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dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)]
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dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map.extend(list(zip(bank_pins, dff_pins)))
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if self.num_wmasks > 0 and port in self.write_ports:
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layer_stack = self.m3_stack
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else:
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@ -401,17 +409,17 @@ class sram_1bank(sram_base):
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offset=offset,
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layer_stack=layer_stack)
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# Route these separately because sometimes the pin pitch on the write driver is too narrow for M3 (FreePDK45)
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# spare wen dff
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if self.num_spare_cols > 0 and port in self.write_ports:
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dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)]
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dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names]
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bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)]
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bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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route_map = zip(bank_pins, dff_pins)
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self.create_horizontal_channel_route(netlist=route_map,
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offset=offset,
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layer_stack=self.m1_stack)
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# # Route these separately because sometimes the pin pitch on the write driver is too narrow for M3 (FreePDK45)
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# # spare wen dff
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# if self.num_spare_cols > 0 and port in self.write_ports:
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# dff_names = ["dout_{}".format(x) for x in range(self.num_spare_cols)]
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# dff_pins = [self.spare_wen_dff_insts[port].get_pin(x) for x in dff_names]
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# bank_names = ["bank_spare_wen{0}_{1}".format(port, x) for x in range(self.num_spare_cols)]
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# bank_pins = [self.bank_inst.get_pin(x) for x in bank_names]
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# route_map = zip(bank_pins, dff_pins)
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# self.create_horizontal_channel_route(netlist=route_map,
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# offset=offset,
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# layer_stack=self.m1_stack)
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def route_clk(self):
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""" Route the clock network """
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