mirror of https://github.com/VLSIDA/OpenRAM.git
Change col addr spacing to col addr size
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@ -320,7 +320,7 @@ class sram_1bank(sram_base):
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""" Connect the output of the col flops to the bank pins """
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for port in self.all_ports:
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if port%2:
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offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.word_size+2)*self.m1_pitch)
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offset = self.col_addr_dff_insts[port].ll() - vector(0, (self.col_addr_size+2)*self.m1_pitch)
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else:
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offset = self.col_addr_dff_insts[port].ul() + vector(0, 2*self.m1_pitch)
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