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OpenRAM
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Add data bus gap to dynamically computed channel width

This commit is contained in:
mrg 2020-07-20 13:43:57 -07:00
parent a36e89e103
commit 82bbacdfb5
1 changed files with 2 additions and 2 deletions
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4
compiler/sram/sram_1bank.py
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@ -465,7 +465,7 @@ class sram_1bank(sram_base):
self.add_inst("hc", cr)
self.connect_inst([])
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port])
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
else:
offset = vector(0,
self.bank.height + 2 * self.m1_space)
@ -477,7 +477,7 @@ class sram_1bank(sram_base):
self.add_inst("hc", cr)
self.connect_inst([])
else:
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port])
self.data_bus_size[port] = max(cr.height, self.col_addr_bus_size[port]) + self.data_bus_gap
def route_clk(self):
""" Route the clock network """