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begin fixes to pbitcell, prepare multibank pex

This commit is contained in:
Jesse Cirimelli-Low 2020-01-24 10:24:29 +00:00
parent 40c01dab85
commit 1062cbfd7f
3 changed files with 67 additions and 37 deletions
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24
compiler/base/geometry.py
View File

@ -321,7 +321,7 @@ class instance(geometry):
cell_paths.append(copy.copy(path))
normalized_storage_nets = node.mod.get_normalized_storage_nets_offset()
normalized_bitline_nets = node.mod.get_normalized_bitline_offset()
(normalized_bl_offsets, normalized_br_offsets) = node.mod.get_normalized_bitline_offset()
Q_x = normalized_storage_nets[0][0]
Q_y = normalized_storage_nets[0][1]
@ -329,22 +329,26 @@ class instance(geometry):
Q_bar_x = normalized_storage_nets[1][0]
Q_bar_y = normalized_storage_nets[1][1]
bl_x = normalized_bitline_nets[0][0]
bl_y = normalized_bitline_nets[0][1]
br_x = normalized_bitline_nets[1][0]
br_y = normalized_bitline_nets[1][1]
if node.mirror == 'MX':
Q_y = -1 * Q_y
Q_bar_y = -1 * Q_bar_y
bl_y = -1 * bl_y
br_y = -1 * br_y
for pair in range(len(normalized_bl_offsets)):
for offset in range(len(offset)):
normalized_bl_offsets[pair][offset] = -1 * normalized_bl_offsets[pair][offset]
for pair in range(len(normalized_br_offsets)):
for offset in range(len(offset)):
normalized_br_offsets[pair][offset] = -1 * normalized_br_offsets[pair][offset]
Q_offsets.append([Q_x, Q_y])
Q_bar_offsets.append([Q_bar_x, Q_bar_y])
bl_offsets.append([bl_x, bl_y])
br_offsets.append([br_x, br_y])
for offset in bl_offset:
bl_offsets.append(offset)
for offset in br.offset:
br_offsets.append(offset)
elif node.mod.insts is not []:
for instance in node.mod.insts:

44
compiler/bitcells/bitcell_base.py
View File

@ -100,21 +100,39 @@ class bitcell_base(design.design):
return(self.storage_net_offsets)
def get_bitline_offset(self):
self.bitline_names = ["bl", "br"]
found_bitlines = []
self.bitline_offsets = []
for i in range(len(self.bitline_names)):
bl_names = self.get_all_bl_names()
br_names = self.get_all_br_names()
found_bl = []
found_br = []
self.bl_offsets = []
self.br_offsets = []
for i in range(len(bl_names)):
for text in self.gds.getTexts(layer["metal2"]):
if not self.bitline_names[i] in found_bitlines:
if self.bitline_names[i] == text.textString.rstrip('\x00'):
self.bitline_offsets.append(text.coordinates[0])
found_bitlines.append(self.bitline_names[i])
if not bl_names[i] in found_bl:
if bl_names[i] == text.textString.rstrip('\x00'):
self.bl_offsets.append(text.coordinates[0])
found_bl.append(bl_names[i])
continue
for i in range(len(self.bitline_offsets)):
self.bitline_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bitline_offsets[i]])
return(self.bitline_offsets)
for i in range(len(br_names)):
for text in self.gds.getTexts(layer["metal2"]):
if not br_names[i] in found_br:
if br_names[i] == text.textString.rstrip('\x00'):
self.br_offsets.append(text.coordinates[0])
found_br.append(br_names[i])
continue
for i in range(len(self.bl_offsets)):
self.bl_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.bl_offsets[i]])
for i in range(len(self.br_offsets)):
self.br_offsets[i] = tuple([self.gds.info["units"][0] * x for x in self.br_offsets[i]])
return(self.bl_offsets, self.br_offsets)
def get_normalized_storage_nets_offset(self):
"""

36
compiler/sram/sram_base.py
View File

@ -104,23 +104,31 @@ class sram_base(design, verilog, lef):
storage_layer_name = "metal1"
bitline_layer_name = "metal2"
for i in range(0,len(bank_offset)):
Q = [bank_offset[i][0] + Q_offset[i][0], bank_offset[i][1] + Q_offset[i][1]]
Q_bar = [bank_offset[i][0] + Q_bar_offset[i][0], bank_offset[i][1] + Q_bar_offset[i][1]]
bl = [bank_offset[i][0] + bl_offsets[i][0], bank_offset[i][1] + bl_offsets[i][1]]
br = [bank_offset[i][0] + br_offsets[i][0], bank_offset[i][1] + br_offsets[i][1]]
Q = [bank_offset[bank_num][0] + Q_offset[bank_num][0], bank_offset[bank_num][1] + Q_offset[bank_num][1]]
Q_bar = [bank_offset[bank_num][0] + Q_bar_offset[bank_num][0], bank_offset[bank_num][1] + Q_bar_offset[bank_num][1]]
bl = []
br = []
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
for i in range(len(bl_offsets)):
bl.append([bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + bl_offsets[bank_num][2*(i)+1]])
if OPTS.num_banks == 1:
for i in range(len(br_offsets)):
br.append([bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)], bank_offset[bank_num][1] + br_offsets[bank_num][2*(i)+1]])
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), storage_layer_name, Q_bar)
if OPTS.num_banks == 1:
for i in range(len(bl_offsets)):
self.add_layout_pin_rect_center("bl_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
for i in range(len(br_offsets)):
self.add_layout_pin_rect_center("br_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
else:
self.add_layout_pin_rect_center("bl{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)) , bitline_layer_name, bl)
self.add_layout_pin_rect_center("br{0}_{2}".format(bank_num, i % OPTS.num_words, int(i / OPTS.num_words)), bitline_layer_name, br)
@ -178,8 +186,8 @@ class sram_base(design, verilog, lef):
highest_coord = self.find_highest_coords()
self.width = highest_coord[0]
self.height = highest_coord[1]
self.add_global_pex_labels()
if OPTS.use_pex:
self.add_global_pex_labels()
start_time = datetime.now()
# We only enable final verification if we have routed the design