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OpenRAM
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262 Commits

Author SHA1 Message Date
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
Jesse Cirimelli-Low a7d0a1ef3a remove breakpoint 2021-05-03 16:54:54 -07:00
Jesse Cirimelli-Low 14e087a5eb offset bank coordinates 2021-05-03 15:51:53 -07:00
mrg a0e263b14a Add vdd/gnd pins to the side. 2021-05-03 15:14:15 -07:00
mrg f45efe3db6 Abstracted LEF added. Params for array wordline layers. 2021-04-21 11:04:01 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg a730fd0f10 Use magic for LEF abstract. Fix supply perimter pin. 2021-04-14 10:01:43 -07:00
mrg e706f776eb Offset macro to 0,0 which was accidentally comented by a PR 2021-04-13 16:24:13 -07:00
mrg 229b0059c4 Add perimeter margin to expand pins outside perimeter for OpenRoad router. 2021-04-07 16:08:29 -07:00
mrg 0a02f635ad Remove lvs_write from sram 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg 13bdae2e30 Merge remote-tracking branch 'private/dev' into control-logic-pull 2021-03-01 15:47:33 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg f31125645e Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2021-03-01 14:06:51 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
mrg 9f0ab0d081 Route perimeter signals before power grid 2021-02-26 11:14:39 -08:00
Hunter Nichols c7f14b1bf9 Removed stale fixme and moved words per row OPTS setting. 2021-02-15 15:20:32 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 6f5b7c0264 Flatten bug fixed in Magic so don't flatten routes. 2021-01-12 16:20:03 -08:00
mrg ec6f0f1873 Escape route to any side 2021-01-06 09:40:32 -08:00
mrg c89e156bfe Separate add pins and route pins so pins can block supply router. 2020-12-23 10:49:47 -08:00
mrg 1885794016 Only write drc/lvs scripts if drc/lvs is enabled 2020-12-23 07:16:43 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg 98250cf115 Copy pins as rects before removing them. 2020-12-21 13:47:05 -08:00
mrg 3c08dfcca5 Enable single pin for vdd/gnd after supply router 2020-12-18 11:09:10 -08:00
mrg c0ab0af201 Retry routes with expanding detour allowed. 2020-12-17 11:39:17 -08:00
mrg d5ed45dadf Make default router tree router 2020-12-16 16:42:19 -08:00
mrg f55b57033d Route col decoder address with data bits in channel 2020-12-15 16:37:23 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg 6714e9fac0 Only run DRC and LVS at SRAM level if not a unit test to reduce run time. 2020-12-15 10:46:55 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 57e708a6e1 Add 200 cycles. Can be commented out or run for shorter. 2020-11-09 15:20:36 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg fa89b73ef8 PR from mithro + other changable GDS file names 2020-11-02 16:00:16 -08:00
Hunter Nichols 12a8531248 Allowed for OPTS writeback of words_per_row if automatically generated during generation. 2020-10-21 03:02:39 -07:00
mrg c2629edc1b Allow 16-way column mux 2020-10-06 16:27:02 -07:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg 60224b105f Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-08-17 14:20:34 -07:00
mrg 50525e70f4 Fix up to SRAM level with new replica bitcell array ports. 2020-08-13 14:29:10 -07:00
mrg 0bec6f0439 Fix SRAM to use simulation spice instead of LVS spice 2020-08-12 10:41:21 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
Bob Vanhoof 9b8ef5ef57 fix: generated pex file was not passed correctly to lib characterizer 2020-08-03 10:16:12 +02:00
mrg 487027a9f2 Fix pex file names 2020-07-30 11:35:13 -07:00
Matt Guthaus 68387ec525
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate 
calibrepex: file copy fix
 2020-07-30 08:40:35 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
Bob Vanhoof ee3da91232 calibrepex: file copy fix 2020-07-15 11:50:21 +02:00
mrg bb8157b3b7 Exit on DRC not run, check for LVSDRC before running in sram_base. 2020-07-14 08:38:49 -07:00
mrg 2011974e01 Make drc and lvs errors a member variable. Run only once. 2020-07-13 12:49:24 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
mrg 8e8a97cc4b Add correct boundary to SRAM 2020-06-14 14:17:35 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00