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OpenRAM
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Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation.

This commit is contained in:
jsowash 2019-08-29 14:48:13 -07:00
parent af3d2af0ec
commit c1906ade3f
2 changed files with 21 additions and 29 deletions
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12
compiler/modules/write_mask_and_array.py
View File

@ -106,6 +106,7 @@ class write_mask_and_array(design.design):
self.nand2 = factory.create(module_type="pnand2")
supply_pin=self.nand2.get_pin("vdd")
# Create the enable pin that connects all write mask AND array's B pins
beg_en_pin = self.and2_insts[0].get_pin("B")
end_en_pin = self.and2_insts[self.num_wmasks-1].get_pin("B")
self.add_layout_pin(text="en",
@ -114,22 +115,17 @@ class write_mask_and_array(design.design):
width = end_en_pin.cx() - beg_en_pin.cx())
for i in range(self.num_wmasks):
# Copy remaining layout pins
self.copy_layout_pin(self.and2_insts[i],"A","wmask_in_{0}".format(i))
wmask_in_pin = self.and2_insts[i].get_pin("A")
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=wmask_in_pin.center())
self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i))
# Add via connections to metal3 for AND array's B pin
en_pin = self.and2_insts[i].get_pin("B")
# Add the M1->M2 stack
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=en_pin.center())
# Add the M2->M3 stack
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=en_pin.center())
self.copy_layout_pin(self.and2_insts[i],"Z","wmask_out_{0}".format(i))
self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))
self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height))
# Route power and ground rails together

38
compiler/sram/sram_1bank.py
View File

@ -77,38 +77,35 @@ class sram_1bank(sram_base):
# Port 0
port = 0
if self.write_size:
if port in self.write_ports:
if port in self.write_ports:
if self.write_size:
# Add the write mask flops below the write mask AND array.
wmask_pos[port] = vector(self.bank.bank_array_ll.x,
-0.5*max_gap_size - self.dff.height)
-0.5 * max_gap_size - self.dff.height)
self.wmask_dff_insts[port].place(wmask_pos[port])
# Add the data flops below the write mask flops.
data_pos[port] = vector(self.bank.bank_array_ll.x,
-1.5*max_gap_size - 2*self.dff.height)
-1.5 * max_gap_size - 2 * self.dff.height)
self.data_dff_insts[port].place(data_pos[port])
else:
wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
data_pos[port] = vector(self.bank.bank_array_ll.x,0)
# Add the data flops below the bank to the right of the lower-left of bank array
# This relies on the lower-left of the array of the bank
# decoder in upper left, bank in upper right, sensing in lower right.
# These flops go below the sensing and leave a gap to channel route to the
# sense amps.
if port in self.write_ports:
data_pos[port] = vector(self.bank.bank_array_ll.x,
-max_gap_size - self.dff.height)
self.data_dff_insts[port].place(data_pos[port])
else:
# Add the data flops below the bank to the right of the lower-left of bank array
# This relies on the lower-left of the array of the bank
# decoder in upper left, bank in upper right, sensing in lower right.
# These flops go below the sensing and leave a gap to channel route to the
# sense amps.
if port in self.write_ports:
data_pos[port] = vector(self.bank.bank_array_ll.x,
-max_gap_size - self.dff.height)
self.data_dff_insts[port].place(data_pos[port])
wmask_pos[port] = vector(self.bank.bank_array_ll.x, 0)
data_pos[port] = vector(self.bank.bank_array_ll.x,0)
else:
data_pos[port] = vector(self.bank.bank_array_ll.x,0)
# Add the col address flops below the bank to the left of the lower-left of bank array
if self.col_addr_dff:
if self.write_size is not None:
if self.write_size:
col_addr_pos[port] = vector(self.bank.bank_array_ll.x - self.col_addr_dff_insts[port].width - self.bank.m2_gap,
-0.5*max_gap_size - self.col_addr_dff_insts[port].height)
else:
@ -145,7 +142,6 @@ class sram_1bank(sram_base):
data_pos[port] = vector(self.bank.bank_array_ur.x - self.data_dff_insts[port].width,
self.bank.height + 1.5*max_gap_size + 2*self.dff.height)
self.data_dff_insts[port].place(data_pos[port], mirror="MX")
else:
# Add the data flops above the bank to the left of the upper-right of bank array
# This relies on the upper-right of the array of the bank
@ -158,7 +154,7 @@ class sram_1bank(sram_base):
# Add the col address flops above the bank to the right of the upper-right of bank array
if self.col_addr_dff:
if self.write_size is not None:
if self.write_size:
col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap,
self.bank.height + 0.5*max_gap_size + self.dff.height)
else: