luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

fix pex for larger memories

This commit is contained in:
jcirimel 2020-05-04 01:31:51 -07:00
parent 6e070925b6
commit 89688f8ea9
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
compiler/sram/sram_base.py
View File

@ -115,8 +115,8 @@ class sram_base(design, verilog, lef):
Q = [bank_offset[cell][0] + Q_offset[cell][0], bank_offset[cell][1] + Q_offset[cell][1]]
Q_bar = [bank_offset[cell][0] + Q_bar_offset[cell][0], bank_offset[cell][1] + Q_bar_offset[cell][1]]
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % OPTS.num_words, int(cell / OPTS.num_words)), storage_layer_name, Q_bar)
self.add_layout_pin_rect_center("bitcell_Q_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))) , storage_layer_name, Q)
self.add_layout_pin_rect_center("bitcell_Q_bar_b{0}_r{1}_c{2}".format(bank_num, cell % (OPTS.num_words * self.words_per_row), int(cell / (OPTS.num_words / self.words_per_row))), storage_layer_name, Q_bar)
for cell in range(len(bl_offsets)):
col = bl_meta[cell][0][2]